ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 366

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.16 Register Description
28.16.1
28.16.2
8331A–AVR–07/11
CTRLA – Control Register A
CTRLB – ADC Control Register B
• Bit 7:6 – DMASEL[1:0]: DMA Request Selection
To allow one DMA channel to serve more than one ADC channel, the DMA request from the
channels can be combined into a common DMA request. See
Table 28-1.
• Bit 5:2 – CHSTART[3:0]: ADC Channel Start single conversion
Setting any of these bits will start a conversion on the corresponding ADC channel. Setting sev-
eral bits at the same time will start conversions on all selected ADC channels, starting with the
channel with lowest number. These bits are cleared by hardware when the conversion has
started.
• Bit 1 – FLUSH: ADC Pipeline Flush:
Setting this bit will flush the ADC pipeline. When this is done the ADC Clock is restarted on the
next Peripheral clock edge and all conversions in progress are aborted and lost.
After the flush and the ADC Clock restart, the ADC will resume where it left off. I.e. if a channel
sweep was in progress or any conversions were pending, these will enter the ADC pipeline and
complete.
• Bit 0 – ENABLE: ADC Enable
Setting this bit enables the ADC.
• Bit 7 – IMPMODE: Gain Stage Impedance Mode
This bit controls the impedance mode of the gain stage. See GAIN setting with ADC Channel
Register description for more information.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
DMASEL[1:0]
–
IMPMODE
ADC
00
01
10
11
R/W
R/W
7
0
7
0
DMA Request Selection
DMASEL[1:0]
R/W
CURRLIMIT[1:0]
R/W
6
0
6
0
Group Configuration
R/W
5
0
R/W
CH0123
5
0
CH012
CH01
OFF
CONVMODE
R/W
R/W
4
0
4
0
CHSTART[3:0]
FREERUN
Description
No combined DMA request
Common request for ADC Channel 0 and 1
Common request for ADC Channel 0, 1 and 2
Common request for ADC Channel 0, 1, 2 and 3
R/W
R/W
Atmel AVR XMEGA AU
3
0
3
0
R/W
R/W
RESOLUTION[1:0]
2
0
2
0
Table 28-1
FLUSH
R/W
R/W
1
0
1
0
for details.
ENABLE
R/W
R
0
0
0
–
0
CTRLA
CTRLB
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