ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 16

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.10
7.11
7.12
7.13
8330B–AVR–10/11
ATxmega64B1
ATxmega128B1
ATxmega64B1
ATxmega128B1
Devices
Devices
Device ID and Revision
JTAG Disable
I/O Memory Protection
Flash and EEPROM Page Size
PC size
(bits)
16
17
EEPROM
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the
device and the device type. A separate register contains the revision number of the device.
It is possible to disable the JTAG interface from the application software. This will prevent all
external JTAG access to the device until the next device reset or until JTAG is enabled again
from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can
be used as normal I/O pins.
Some features in the device are regarded as critical for safety in some applications. Due to this,
it is possible to lock the I/O register related to the clock system, the event system, and the
advanced waveform extensions. As long as the lock is enabled, all related I/O registers are
locked and they can not be written from the application software. The lock registers themselves
are protected by the configuration change protection mechanism.
The flash program memory and EEPROM data memory are organized in pages. The pages are
word accessible for the flash and byte accessible for the EEPROM.
Table 7-2 on page 16
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) give the page number and the least significant address bits (FWORD)
give the word in the page.
Table 7-2.
Table 7-3 on page 16
EEEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM address regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give
the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Size
2K
2K
Flash size
128K + 8K
64K + 4K
(bytes)
Number of words and pages in the flash.
Number of bytes and pages in the EEPROM.
Page Size
(words)
128
256
Page Size
(Bytes)
shows the Flash Program Memory organization. Flash write and erase
32
32
shows EEPROM memory organization for the XMEGA B1 devices.
FWORD
Z[7:1]
Z[8:1]
FPAGE
Z[16:8]
Z[17:9]
ADDR[4:0]
ADDR[4:0]
E2BYTE
128K
Size
64K
Application
ADDR[10:5]
ADDR[10:5]
E2PAGE
No of pages
256
512
XMEGA B1
Size
4K
8K
No of Pages
Boot
64
64
No of pages
16
32
16