ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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This document contains complete and detailed description of all modules included in
the Atmel
family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon-
trollers based on the AVR enhanced RISC architecture. The available Atmel AVR
XMEGA B modules described in this manual are:
Atmel AVR CPU
Memories
DMA - Direct memory access controller
Event system
System clock and clock options
Power management and sleep modes
System control and reset
WDT - Watchdog timer
Interrupts and programmable multilevel interrupt controller
PORT - I/O ports
TC - 16-bit timer/counters
AWeX - Advanced waveform extension
Hi-Res - High resolution extension
RTC - Real-time counter
USB - Universial serial bus interface
TWI - Two-wire serial interface
SPI - Serial peripheral interface
USART - Universal synchronous and asynchronous serial receiver and transmitter
IRCOM - Infrared communication module
AES and DES cryptographic engine
CRC - Cyclic redundancy check
LCD - Liquid Crystal Display
ADC - Analog-to-digital converter
AC - Analog comparator
IEEE 1149.1 JTAG interface
PDI - Program and debug interface
Memory programming
Peripheral address map
Register summary
Interrupt vector summary
Instruction set summary
®
AVR
®
XMEGA
®
B microcontroller family. The Atmel AVR XMEGA B is a
8-bit Atmel
XMEGA B
Microcontroller
XMEGA B
MANUAL
8291A- AVR-10/11

Related parts for ATxmega128B1

ATxmega128B1 Summary of contents

Page 1

This document contains complete and detailed description of all modules included in ® ® ® the Atmel AVR XMEGA B microcontroller family. The Atmel AVR XMEGA family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon- trollers based ...

Page 2

About the Manual This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA B microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and ...

Page 3

Overview The AVR XMEGA B microcontrollers is a family of low-power, high-performance, and peripheral- rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the Atmel AVR XMEGA ...

Page 4

The Atmel AVR XMEGA B devices are supported with a full suite of program and system devel- opment tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 8291A–AVR–10/11 Atmel AVR XMEGA B 4 ...

Page 5

Block Diagram Figure 2-1. Atmel AVR XMEGA B block diagram. PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Refs. Tempref AREFB ADCB ACB PB[0..7]/ PORT B (8) JTAG 8291A–AVR–10/11 PR[0..1] XTAL1 / TOSC1 XTAL2 / TOSC2 Oscillator PORT ...

Page 6

AVR CPU 3.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack pointer accessible in I/O memory space • Direct ...

Page 7

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information ...

Page 8

Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: • Multiplication of unsigned integers • Multiplication of signed ...

Page 9

Figure 3-3 on page 9 cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 3-3. Register Operands Fetch ALU Operation Execute 3.7 Status Register The status register (SREG) ...

Page 10

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer ...

Page 11

Figure 3-5. Bit (individually) X-register Bit (X-register) Bit (individually) Y-register Bit (Y-register) Bit (individually) Z-register Bit (Z-register) The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-significant byte (MSB). In the different addressing ...

Page 12

RAMPD Register This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address. Figure 3-7. Bit (Individually) Bit (D-pointer) 3.10.3 EIND ...

Page 13

This is handled globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or execution of protected instruc- tions, are only possible after the CPU writes a signature to ...

Page 14

Register Descriptions 3.14.1 CCP – Configuration Change Protection Register Bit +0x04 Read/Write Initial Value • Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O ...

Page 15

Bit +0x09 Read/Write Initial Value • Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of bits required to address the available ...

Page 16

EXALL/EIJMP are used, and it will not be used if CALL and IJMP commands are used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program memory in the ...

Page 17

SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. Bit +0x0F Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable ...

Page 18

Register Summary Address Name Bit 7 +0x00 Reserved – +0x01 Reserved – +0x02 Reserved – +0x03 Reserved – +0x04 CCP +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – +0x08 RAMPD +0x09 RAMPX +0x0A RAMPY +0x0B RAMPZ +0x0C EIND ...

Page 19

Memories 4.1 Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot ...

Page 20

All AVR CPU instructions are bit wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section, as shown in dependent. These ...

Page 21

The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section ...

Page 22

Figure 4-2. I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices. 4.6 Internal SRAM The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the CPU using the load (LD/LDS/LDD) ...

Page 23

Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus mas- ters (CPU, DMA controller read and DMA controller write, etc.) can access different memories at the same time. ...

Page 24

Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 4.12 JTAG Disable It ...

Page 25

Register Description – NVM Controller – 4.14.1 ADDR0 Address Register 0 The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value ADDR. This is used for addressing all NVM sections for read, write, and CRC operations. Bit +0x00 Read/Write ...

Page 26

DATA1 – Data Register 1 Bit +0x05 Read/Write Initial Value • Bit 7:0 – DATA[15:8]: Data Register Byte 1 This register gives the data value byte 1 when accessing NVM locations. 4.14.6 DATA2 – Data Register Byte 2 Bit ...

Page 27

Bit 0 – CMDEX: Command Execute Setting this bit will execute the command in the CMD register. This bit is protected by the config- uration change protection (CCP) mechanism, refer to page 12 4.14.9 CTRLB – Control Register B ...

Page 28

Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level These bits enable the interrupt and select the interrupt level, as described in grammable Multilevel Interrupt Controller” on page triggered when the BUSY flag in the STATUS is set to zero. ...

Page 29

LOCKBITS – Lock Bit Register Bit +0x07 Read/Write Initial Value This register is a mapping of the NVM lockbits into the I/O memory space, enable direct read access from the application software. Refer to description. 4.15 Register Descriptions – ...

Page 30

FUSEBYTE2 – Fuse Byte 2 Bit +0x02 Read/Write Initial Value • Bit 7 – Reserved This fuse bit is reserved. For compatibility with future devices, always write this bit to one when this register is written. • Bit 6 ...

Page 31

FUSEBYTE4 – Fuse Byte 4 Bit +0x04 Read/Write Initial Value • Bit 7:5 – Reserved These fuse bits are reserved. For compatibility with future devices, always write these bits to one when this register is written. • Bit: 4 ...

Page 32

JTAG interface. A reset is required before this bit will be read correctly after it is changed. Table 4-6. JTAGEN 4.15.5 FUSEBYTE5 – Fuse Byte 5 Bit +0x05 Read/Write Initial Value • Bit 7:6 – Reserved These bits ...

Page 33

Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level These fuse bits sets the BOD voltage level. Refer to BOD level nominal values, see 4.15.6 LOCKBITS – Lock Bit Register Bit +0x07 Read/Write Initial Value • Bit 7:6 – BLBB[1:0]: ...

Page 34

Table 4-10. BLBA[1:0] • Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section These lock bits control the security level for the application table section. The BLBAT bits can only be written to a more strict locking. Resetting the ...

Page 35

Bit 1:0 – LB[1:0]: Lock Bits These lock bits control the the security level for the flash and EEPROM during external program- ming. These bits are writable only through an external programming interface. Resetting the lock bits is possible ...

Page 36

RCOSC32K – Internal 32.768kHz Oscillator Calibration Register Bit +0x02 Read/Write Initial Value • Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibra- tion of the oscillator ...

Page 37

LOTNUM0 – Lot Number Register 0 LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4 and LOTNUM5 contain the lot num- ber for each device. Together with the wafer number and wafer coordinates this gives a serial number for the device. Bit +0x08 ...

Page 38

LOTNUM4 – Lot Number Register 4 Bit +0x0C Read/Write Initial Value • Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4 This byte contains byte 4 of the lot number for the device. 4.16.11 LOTNUM5 – Lot Number Register 5 ...

Page 39

COORDX1 – Wafer Coordinate X Register 1 Bit +0x13 Read/Write Initial Value • Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device. 4.16.15 COORDY0 – Wafer Coordinate ...

Page 40

USBCAL1 – USB Pad Calibration Register 1 Bit +0x1B Read/Write Initial Value • Bit 7:0 – USBCAL1[7:0]: USB Pad Calibration Register 1 This byte contains byte 1 of the USB pin calibration data, and must be loaded into the ...

Page 41

Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register. 4.16.22 ADCBCAL0 – ADCB Calibration Register 0 ADCBCAL0 and ADCBCAL1 contains the ...

Page 42

TEMPSENSE1 – Temperature Sensor Calibration Register 1 Bit +0x2F Read/Write Initial Value • Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1 This byte contains byte 1 of the temperature measurement. 4.17 Register Description – General Purpose I/O Memory ...

Page 43

DEVID2 – Device ID Register 2 Bit +0x02 Read/Write Initial Value • Bit 7:0 – DEVID2[7:0]: Device ID Byte 2 Byte 2 of the device ID indicates the device number. 4.18.4 REVID – Revision ID Bit +0x03 Read/Write Initial ...

Page 44

Bit 0 – JTAGD: JTAG Disable Setting this bit will disable the JTAG interface. This bit is protected by the configuration change protection mechanism or details refer to 4.18.7 ANAINIT – Analog Initialization Register Bit +0x07 Read/Write Initial Value ...

Page 45

AWEXLOCK – Advanced Waveform Extension Lock Register Bit +0x09 Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...

Page 46

Register Summary - NVM Controller Address Name Bit 7 +0x00 ADDR0 +0x01 ADDR1 +0x02 ADDR2 +0x03 Reserved – +0x04 DATA0 +0x05 DATA1 +0x06 DATA2 +0x07 Reserved – +0x08 Reserved – +0x09 Reserved – +0x0A CMD – +0x0B CTRLA – ...

Page 47

Register Summary - Production Signature Row Address Auto Load Name +0x00 YES RCOSC2M +0x01 YES RCOSC2MA +0x02 YES RCOSC32K +0x03 YES RCOSC32M +0x04 YES RCOSC32MA +0x05 Reserved +0x06 Reserved +0x07 Reserved +0x08 NO LOTNUM0 +0x09 NO LOTNUM1 +0x0A NO ...

Page 48

Register Summary - General Purpose I/O Registers Address Name Bit 7 +0x00 GPIOR0 +0x01 GPIOR1 +0x02 GPIOR2 +0x03 GPIOR3 +0x04 Reserved – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – +0x08 Reserved – +0x09 Reserved – +0x0A Reserved ...

Page 49

DMAC - Direct Memory Access Controller 5.1 Features • Allows high speed data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from ...

Page 50

Figure 5-1. 5.3 DMA Transaction A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction. A transaction is done in data blocks, and the size of the transaction (number of bytes to transfer) is ...

Page 51

Figure 5-2. 5.4 Transfer Triggers DMA transfers can be started only when a DMA transfer request is detected. A transfer request can be triggered from software, from an external trigger source (peripheral), or from an event. There are dedicated source ...

Page 52

A round robin scheme means that the channel that last transferred data will have the lowest priority. 5.7 Double Buffering To allow ...

Page 53

Interrupts The DMA controller can generate interrupts when an error is detected on a DMA channel or when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt vector, and there are different interrupt ...

Page 54

Register Description – DMA Controller 5.13.1 CTRL – Control Register Bit +0x00 Read/Write Initial Value • Bit 7 – ENABLE: Enable Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written ...

Page 55

INTFLAGS – Interrupt Status Register Bit +0x03 Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to one when this register is ...

Page 56

TEMP – Temporary Register Bit +0x06 Read/Write Initial Value • Bit 7:0 – TEMP[7:0]: Temporary Register This register is used when reading 16-bit registers in the DMA controller. Byte 1 of the 16-bit reg- ister is stored here when ...

Page 57

Bit 2 – SINGLE: Single-Shot Data transfer Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. A write to this bit will be ignored while the ...

Page 58

CTRLB – Control Register B Bit +0x04 Read/Write Initial Value • Bit 7 – CHBUSY - Busy When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag is automatically cleared when ...

Page 59

Bit 7:6 – SRCRELOAD[1:0]: Source Address Reload These bits decide the DMA channel source address reload according to these bits is ignored while the channel is busy. Table 5-5. SRCRELOAD[1:0] • Bit 5:4 – SRCDIR[1:0]: Source Address Mode These ...

Page 60

Table 5-8. DESTDIR[1:0] 5.14.4 TRIGSRC – Trigger Source Register Bit +0x03 Read/Write Initial Value • Bit 7:0 – TRIGSRC[7:0]: Trigger Source Select These bits select which trigger source is used for triggering a transfer on the DMA channel. A zero ...

Page 61

Table 5-9. TRIGSRC Base Value Table 5-10. TRGSRC Offset Value Table 5-11. TRGSRC offset value Table 5-12. TRGSRC Offset Value Note: Table 5-13. TRGSRC Offset Value The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1 CC ...

Page 62

DMA channel. When TRFCNT reaches zero, the register is reloaded with the last value written to it. Bit +0x04 Read/Write Initial Value • Bit 7:0 – TRFCNT[7:0]: Block Transfer Count Register Low byte These bits hold ...

Page 63

SRCADDR0 – Source Address byte 0 SRCADDR0 and SRCADDR1 represent the 16-bit value SRCADDR, which is the DMA channel source address. SRCADDR1 is the most significant byte in the register. SRCADDR may be automatically incremented or decremented based on ...

Page 64

Register Summary – DMA Controller Address Name Bit 7 +0x00 CTRL ENABLE +0x01 Reserved – +0x02 Reserved – +0x03 INTFLAGS – +0x04 STATUS – +0x05 Reserved – +0x06 TEMP +0x07 Reserved – +0x10 CH0 Offset +0x20 CH1 Offset +0x30 ...

Page 65

Event System 6.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed ...

Page 66

The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is two peripheral ...

Page 67

Event users that can utilize data events can also use signaling events. This is configurable, and is described in the datasheet module for each peripheral. 6.3.3 Peripheral Clock Events Each event channel includes a peripheral clock prescaler with a range ...

Page 68

Figure 6-3. Four multiplexers means that it is possible to route up to four events at the same time also possible to route one event through several multiplexers. Not all XMEGA devices contain all peripherals. This only means ...

Page 69

Quadrature Decoder The event system includes one quadrature decoder (QDEC), which enable the device to decode quadrature input on I/O pins and send data events that a timer/counter can decode to count up, count down, or index/reset. events are ...

Page 70

QDEC Setup For a full QDEC setup, the following is required: • Two or three I/O port pins for quadrature signal input • Two event system channels for quadrature decoding • One timer/counter for up, down, and optional index ...

Page 71

Register Description 6.8.1 CHnMUX – Channel n Multiplexer Register Bit Read/Write Initial Value • Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer These bits select the event source according to devices regardless of whether the peripheral is present or not. Selecting ...

Page 72

Table 6-3. CHnMUX[7:4] 0010 0010 0010 0010 0010 0011 0100 0101 0101 0110 0110 0110 0110 0111 0111 1000 1001 1010 1011 1100 1100 1101 1110 1110 1111 Notes: Table 6-4. T/C Event ...

Page 73

CHnCTRL – Channel n Control Register Bit Read/Write Initial Value • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is ...

Page 74

Table 6-6. DIGFILT[2:0] 6.8.3 STROBE – Strobe Register Bit +0x10 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...

Page 75

Register Summary Address Name Bit 7 +0x00 CH0MUX +0x01 CH1MUX +0x02 CH2MUX +0x03 CH3MUX +0x04 Reserved – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – +0x08 CH0CTRL – +0x09 CH1CTRL – +0x0A CH2CTRL – +0x0B CH3CTRL – +0x0C ...

Page 76

System Clock and Clock Options 7.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) ...

Page 77

Figure 7-1. The clock system, clock sources, and clock distribution. Real Time LCD Brown-out Watchdog Detector Timer 32kHz Int. ULP 8291A–AVR–10/11 Peripherals Peripherals Counter clk clk RTC clk PER2 clk LCD clk PER4 RTCSRC XOSCSEL 32.768kHz 32.768kHz Int. OSC TOSC ...

Page 78

Clock Distribution Figure 7-1 on page 77 7.3.1 System Clock - Clk SYS The system clock is the output from the main system clock selection. This is fed into the prescal- ers that are used to generate all internal ...

Page 79

Calibrated Oscillator This oscillator provides an approximate 32.768kHz clock calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the ...

Page 80

Figure 7-3. 7.4.2.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in ure 7-4 on page oscillator can ...

Page 81

Figure 7-5. System clock selection and prescalers. Clock Selection Internal 32.768kHz Osc. Internal 2MHz Osc. Internal 32MHz Osc. Clk SYS Internal PLL. External Oscillator or Clock. Prescaler A divides the system clock, and the resulting clock is clk be enabled ...

Page 82

DFLL 2MHz and DFLL 32MHz Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to ...

Page 83

The value that should be written to the COMP register is given by the following formula: When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the internal oscillator runs too ...

Page 84

It cannot be used for slower external clocks. When the failure monitor is enabled, it will not be disabled until the next reset. The failure monitor is stopped in all ...

Page 85

Register Description - Clock 7.9.1 CTRL – Control Register Bit +0x00 Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero ...

Page 86

Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to can be written at run-time to change the frequency of the Clk clock, Clk Table 7-2. PSADIV[4:0] • ...

Page 87

LOCK – Lock Register Bit +0x02 Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. ...

Page 88

Bit 0 – RTCEN: RTC and LCD Clock Source Enable Setting the RTCEN bit enables the selected clock source for the real-time counter (RTC) and LCD. 7.9.5 USBSCTRL – USB Control Register Bit +0x04 Read/Write Initial Value • Bit ...

Page 89

Register Description — Oscillator 7.10.1 CTRL – Control Register Bit +0x00 Read/Write Initial Value • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero ...

Page 90

Bit 3 – XOSCRDY: External Clock Source Ready This flag is set when the external clock source is stable and is ready to be used as the system clock source. • Bit 2 – RC32KRDY: 32.768kHz Internal Oscillator Ready ...

Page 91

This configuration cannot be changed. Table 7-8. XOSCSEL[4: Notes: 7.10.4 XOSCFAIL – XOSC Failure Detection Register Bit +0x03 Read/Write Initial Value • Bit 7:4 – Reserved ...

Page 92

This bit is protected by the configuration change protection mechanism. Refer to Change Protection” on page reset. 7.10.5 RC32KCAL – 32kHz Oscillator Calibration Register Bit +0x04 Read/Write Initial Value • Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator ...

Page 93

DFLLCTRL – DFLL Control Register Bit +0x06 Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is ...

Page 94

CALA – Calibration Register A The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic run-time calibration of the internal oscillator. When the DFLL is disabled, the calibration registers can be written by ...

Page 95

COMP1 – Compare Register Byte 1 The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The initial value for these registers is the ratio between the internal oscillator frequency and a ...

Page 96

Register Summary - Clock Address Name Bit 7 +0x00 CTRL – +0x01 PSCTRL – +0x02 LOCK – +0x03 RTCCTRL – +0x04 USBSCTRL – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – 7.13 Register Summary - Oscillator Address Name ...

Page 97

Power Management and Sleep Modes 8.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable ...

Page 98

Table 8-1 on page 98 and wake-up sources. Table 8-1. Sleep Modes Idle Power down Power save Standby Extended standby The wake-up time for the device is dependent on the sleep mode and the main clock source. The startup time ...

Page 99

Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC/LCD clocks are stopped. This reduces the wake-up time. 8.3.5 Extended Standby Mode ...

Page 100

Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and, hence, always consume power. Refer to ...

Page 101

Register Description – Sleep 8.6.1 CTRL – Control Register Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero ...

Page 102

Bit 7 – LCD: LCD Module Setting this bit stops the clock to the LCD module. When the bit is cleared the peripheral should be reinitialized to ensure proper operation. • Bit 6 – USB: USB Module Setting this ...

Page 103

Bit 0 – AC: Power Reduction Analog Comparator Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown. 8.7.3 PRPC/E – Power Reduction Port C/E Register Bit +0x03/+0x04/ +0x05/+0x06 Read/Write Initial Value ...

Page 104

Register Summary - Sleep Address Name Bit 7 +0x00 CTRL – 8.9 Register Summary - Power Reduction Address Name Bit 7 +0x00 PRGEN LCD +0x01 PRPA – +0x02 PRPB – +0x03 PRPC – +0x04 Reserved – +0x05 PRPE – ...

Page 105

Reset System 9.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset – Brownout ...

Page 106

Figure 9-1. 9.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through ...

Page 107

Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for Clk 9.3.2 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values ...

Page 108

When the BOD is enabled and V 9-4), the brownout reset is immediately activated. When V MCU after the timeout period, t The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level ...

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Enabled: In this mode, the V for a period of t • Sampled: In this mode, the BOD circuit will sample the V that of the 1kHz output from the ultra low power (ULP) internal oscillator. Between each sample, ...

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Figure 9-6. For information on configuration and use of the WDT, refer to the page 127. 9.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the soft- ware reset bit ...

Page 111

Register Description 9.5.1 STATUS – Status register Bit +0x00 Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...

Page 112

Register Summary Address Name Bit 7 +0x00 STATUS – +0x01 CTRL – 8291A–AVR–10/11 Bit 6 Bit 5 Bit 4 Bit 3 – SRF PDIRF WDRF – – – Atmel AVR XMEGA B Bit 2 Bit 1 Bit 0 BORF ...

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WDT – Watchdog Timer 10.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator • 11 ...

Page 114

Figure 10-1. Normal mode operation. 10.4 Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window time- out period (TO defines a duration of from 8ms to 8s where the WDT cannot be ...

Page 115

Configuration Protection and Lock The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings. The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the WDT control ...

Page 116

Table 10-1. PER[3:0] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 • Bit 1 – ENABLE: Enable This bit enables the WDT. Clearing this bit disables the watchdog timer. In order to change this bit, the CEN bit ...

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In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by the configuration change protection mechanism. For a detailed description, refer to Table 10-2. WPER[3:0] 0000 0001 0010 ...

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Bit 0 – SYNCBUSY: Synchronization Busy Flag This flag is set after writing to the CTRL or WINCTRL registers and the data are being synchro- nized from the system clock to the WDT clock domain. This bit is automatically ...

Page 119

Interrupts and Programmable Multilevel Interrupt Controller 11.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address ...

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Operation Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable ( I ) bit in the CPU status register. The I bit will not be cleared when an ...

Page 121

NMI – Non-Maskable Interrupts Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non- maskable interrupts must be enabled before they can be used. Refer to the device datasheet for NMI present on each device. An ...

Page 122

Figure 11-2. Interrupt execution of a multicycle instruction interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock cycles. In addition, the response time is increased by the start-up ...

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Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre- sponding bit values for the interrupt level ...

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Figure 11-3. Static priority. 11.6.2 Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the ...

Page 125

Interrupt vector locations Table 11-2 on page 125 tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This ...

Page 126

INTPRI – Interrupt priority register Bit +0x01 Read/Write Initial Value • Bit 7:0 – INTPRI: Interrupt Priority When round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged low-level interrupt. The stored interrupt vector will ...

Page 127

Bit 0 – LOLVLEN: Low-level Interrupt Enable When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt requests will be ignored. Note: 11.9 Register Summary Address Name Bit 7 +0x00 STATUS NMIEX ...

Page 128

I/O Ports 12.1 Features • General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O • Input with synchronous and/or ...

Page 129

Figure 12-1 on page 129 controlling a pin. Figure 12-1. General I/O pin functionality. 12.3 I/O Pin Use and Configuration Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port ...

Page 130

The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration also possible to enable inverted input and output for a pin. A totem-pole ...

Page 131

Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull- up when set as input. Figure 12-4. I/O pin configuration - Totem-pole with pull-up (on input). 12.3.2 Bus-keeper In ...

Page 132

Figure 12-6. Output configuration - Wired-OR with optional pull-down. 12.3.4 Wired-AND In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are written to zero. When the OUT register is ...

Page 133

Figure 12-8. Synchronization when reading a pin value. SYNCHRONIZER FLIPFLOP 12.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin ...

Page 134

Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts must be enabled before they can be used. Which sense configurations can be used to generate ...

Page 135

Table 12-3. Sense Settings Rising edge Falling edge Both edges Low level 12.7 Port Event Port pins can generate an event when there is a change on the pin. The sense configurations decide the conditions for each pin to generate ...

Page 136

Figure 12-10. Port override signals and related logic. 12.9 Slew Rate Control Slew rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will typically increase the rise/fall time by 50% to 150%, depending on ...

Page 137

Multi-pin configuration The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the port pin configuration registers. A mask register decides which port pin is configured when one port ...

Page 138

Register Descriptions – Ports 12.13.1 DIR – Data Direction Register Bit +0x00 Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written ...

Page 139

Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. ...

Page 140

OUTTGL – Data Output Value Toggle Register Bit +0x07 Read/Write Initial Value • Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins. ...

Page 141

Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port ...

Page 142

Bit 4 – USART0: USART0 Remap Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4]. • Bit 3 – TC0D: Timer/Counter 0 Output Compare D Setting this bit will move the location ...

Page 143

Table 12-4. OPC[2:0] 000 001 010 011 100 101 110 111 • Bit 2:0 – ISC[2:0]: Input/Sense Configuration These bits set the input and sense configuration on pin n according to configuration decides how the pin can trigger port interrupts ...

Page 144

Register Descriptions – Port Configuration 12.14.1 MPCMASK – Multi-pin Configuration Mask Register Bit +0x00 Read/Write Initial Value • Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same ...

Page 145

Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing ...

Page 146

Table 12-7 on page 146 Table 12-7. EVOUT[1:0] • Bits 3:2 – CLKOUTSEL[1:0] : Clock Output Select These bits are used to select which of the peripheral clocks will be output to the port pin if CLK- OUT is configured. ...

Page 147

Bit 1:0 – EVOUTSEL[1:0]: Event Channel Output Selection These bits define which channel from the event system is output to the port pin. page 147 Table 12-10. Event channel output selection. EVOUTSEL[1:0] 8291A–AVR–10/11 shows the available selections. Group Configuration ...

Page 148

Register Descriptions – Virtual Port 12.15.1 DIR - Data Direction Bit +0x00 Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by VPCTRLA, ...

Page 149

INTFLAGS – Interrupt Flag Register Bit +0x03 Read/Write Initial Value • Bit 7:2 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...

Page 150

Register Summary – Ports Address Name Bit 7 +0x00 DIR +0x01 DIRSET +0x02 DIRCLR +0x03 DIRTGL +0x04 OUT +0x05 OUTSET +0x06 OUTCLR +0x07 OUTTGL +0x08 IN +0x09 INTCTRL – +0x0A INT0MASK +0x0B INT1MASK +0x0C INTFLAGS – +0x0D Reserved – ...

Page 151

TC0/1 – 16-bit Timer/Counter Type 0 and 1 13.1 Features • 16-bit timer/counters • 32-bit timer/counter support by cascading two timer/counters • four compare or capture (CC) channels – Four CC channels for timer/counters of type 0 ...

Page 152

There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only ...

Page 153

When used for capture operations, the CC channels are referred to as “capture channels.” 13.3 Block Diagram Figure 13-2 on page 153 extensions. Figure 13-2. Timer/counter block diagram. The counter register (CNT), period registers with buffer (PER and ...

Page 154

A prescaled peripheral clock and events from the event system can be used to control the coun- ter. The event system is also used as a source to the input capture. Combined with the quadrature decoding functionality in the event ...

Page 155

Figure 13-4. Period and compare double buffering. When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case the buffer valid flag is set on the capture event, as shown ...

Page 156

Figure 13-6. Normal operation. CNT DIR As shown in The write access has higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed during normal operation. Normal operation must be ...

Page 157

A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in and if a new TOP value that is lower than current CNT is written to PER, it will wrap before a compare match ...

Page 158

Figure 13-10. Event source selection for capture operation. Event System The event action setting in the timer/counter will determine the type of capture that is done. The CC channels must be enabled individually before capture can be done. When the ...

Page 159

This can be used to calculate the frequency (f) of the signal Figure 13-12 on page 159 twice. Figure 13-12. Frequency capture of an external signal. external signal ...

Page 160

Figure 13-13. Pulse width capture of an external signal. external signal events CNT 13.7.4 32-bit Input Capture Two timer/counters can be used together to enable true 32-bit input capture typical 32-bit input capture setup, the overflow event of ...

Page 161

The CC channels used must be enabled. This will override the corresponding port pin output register. 4. The direction for the associated port pin must be set to output. Inverted waveform output is achieved by setting the invert output ...

Page 162

Figure 13-15. Single-slope pulse width modulation. CNT WG Output The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX). The following equation calculate the exact resolution for single-slope ...

Page 163

Figure 13-16. Dual-slope pulse width modulation. CNT WG Output Using dual-slope PWM results in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits ...

Page 164

Figure 13-17. Port override for timer/counter 0 and 1. 13.9 Interrupts and events The timer/counter can generate both interrupts and events. The counter can generate an inter- rupt on overflow/underflow, and each CC channel has a separate interrupt that is ...

Page 165

Register Description 13.12.1 CTRLA – Control register A Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when ...

Page 166

Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits ...

Page 167

CTRLD – Control register D Bit +0x03 Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to page 167. The EVSEL setting will decide ...

Page 168

Table 13-6. EVSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 10nn 11xx 13.12.5 CTRLE – Control register E Bit +0x04 Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility ...

Page 169

Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits ...

Page 170

Table 13-8. CMD • Bit 1 – LUPD: Lock Update When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has occurred. Locking the update ensures that all ...

Page 171

INTFLAGS – Interrupt Flag register Bit +0x0C Read/Write Initial Value • Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match input ...

Page 172

For more details, refer to Bit +0x0F Read/Write Initial Value 13.12.12 CNTL – Counter register L The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the timer/counter. CPU and DMA write ...

Page 173

PERH – Period register H Bit +0x27 Read/Write Initial Value • Bit 7:0 – PER[15:8] These bits hold the MSB of the 16-bit period register. 13.12.16 CCxL – Compare or Capture x register L The CCxH and CCxL register ...

Page 174

Bit 7:0 – PERBUF[7:0] These bits hold the LSB of the 16-bit period buffer register. 13.12.19 PERBUFH – Timer/Counter Period Buffer H Bit +0x37 Read/Write Initial Value • Bit 7:0 – PERBUF[15:8] These bits hold the MSB of the ...

Page 175

Register Summary Address Name Bit 7 +0x00 CTRLA – +0x01 CTRLB CCDEN +0x02 CTRLC – +0x03 CTRLD +0x04 CTRLE – +0x05 Reserved – +0x06 INTCTRLA – +0x07 INTCTRLB CCCINTLVL[1:0] +0x08 CTRLFCLR – +0x09 CTRLFSET – +0x0A CTRLGCLR – +0x0B ...

Page 176

TC2 –16-bit Timer/Counter Type 2 14.1 Features • A system of two eight-bit timer/counters – Low-byte timer/counter – High-byte timer/counter • Eight compare channels – Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte ...

Page 177

Block Diagram Figure 14-1. Block diagram of the 16-bit timer/counter 0 with split mode. 14.4 Clock Sources The timer/counter can be clocked from the peripheral clock (clk Figure 14-2 8291A–AVR–10/11 Base Counter HPER LPER Counter HCNT LCNT = 0 ...

Page 178

Figure 14-2. Clock selection. The peripheral clock (clk a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the whole range of time prescalings from The clock selection (CLKSEL) selects one ...

Page 179

Figure 14-4. Changing the period. CNT 14.6 Compare Channel Each compare channel continuously compares the counter value with the CMPx register. If CNT equals CMPx, the comparator signals a match. For the low-byte timer/counter, the match will set the compare ...

Page 180

The PER register defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the maximum resolution is eight bits (PER=MAX). The following equation is used to calculate the exact resolution for a single-slope PWM (R PWM_SS R PWM_SS ...

Page 181

DMA Support Timer/counter underflow and compare interrupt flags can trigger a DMA transaction. The acknowledge condition that clears the flag/request is listed in Table 14-1. Request LUNFIF HUNFIF CCIF{D,C,B,A} 14.9 Timer/Counter Commands A set of commands can be given ...

Page 182

Register Description 14.10.1 CTRLA — Control register A Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when ...

Page 183

CTRLC — Control register C Bit +0x02 Read/Write Initial Value • Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF. This is ...

Page 184

Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level These bits enable the high-byte timer underflow interrupt and select the interrupt level, as described in enabled interrupt will be triggered when HUNFIF in the INTFLAGS register is set. • ...

Page 185

Bit 1:0 – CMDEN[1:0]: Command Enable These bits are used to indicate for which timer/counter the command (CMD) is valid. Table 14-5. CMD 14.10.8 INTFLAGS — Interrupt Flag register Bit +0x0C Read/Write Initial Value • ...

Page 186

HCNT – High-byte Count register Bit +0x21 Read/Write Initial Value • Bit 7:0 – HCNT[7:0] HCNT contains the eight-bit counter value for the high-byte timer/counter. The CPU and DMA write accesses have priority over count, clear, or reload of ...

Page 187

HCMPx – High-byte Compare register x Bit Read/Write Initial Value • Bit 7:0 – HCMPx[7:0], x=[ HCMPx contains the eight-bit compare value for the high-byte timer/counter. These registers are all continuously compared to the counter value. ...

Page 188

Register Summary Address Name Bit 7 +0x00 CTRLA – +0x01 CTRLB HCMPDEN +0x02 CTRLC HCMPD +0x03 Reserved – +0x04 CTRLE – +0x05 Reserved – +0x06 INTCTRLA – +0x07 INTCTRLB LCMPDINTLVL[1:0] +0x08 Reserved – +0x09 CTRLF – +0x0A Reserved – ...

Page 189

AWeX – Advanced Waveform Extension 15.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time ...

Page 190

WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal ...

Page 191

Figure 15-2. Timer/counter extensions and port override logic. 15.4 Dead-time Insertion The dead-time insertion (DTI) unit generates OFF time where the non-inverted low side (LS) and inverted high side (HS) of the WG output are both low. This OFF time ...

Page 192

The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. four channels have a common register that controls the dead time. The high side and low side have independent dead-time setting, and the ...

Page 193

A block diagram of the pattern generator is shown in on page put the waveform from CCA. Figure 15-5. Pattern generator block diagram. As with the other timer/counter double buffered registers, the register update is synchronized to the UPDATE ...

Page 194

Fault Restore Modes How the AWeX and timer/counter return from the fault state to normal operation after a fault, when the fault condition is no longer active, can be selected from one of two different modes: • In latched ...

Page 195

Register Description 15.7.1 CTRL – Control register Bit +0x00 Read/Write Initial Value • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...

Page 196

Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 4 – FDDBD: Fault Detection on Debug Break ...

Page 197

Bit 2 – FDF: Fault Detect Flag This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels enabled by FDEVMASK. This flag is cleared by writing ...

Page 198

Bit 7:0 – DTLS: Dead-time Low Side This register holds the number of peripheral clock cycles for the dead-time low side. 15.7.8 DTHS – Dead-time High Side register Bit +0x09 Read/Write Initial Value • Bit 7:0 – DTHS: Dead-time ...

Page 199

Bit 7:0 – OUTOVEN[7:0]: Output Override Enable These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position). The port direction is not overridden. 15.8 Register Summary Address Name Bit 7 +0x00 CTRL ...

Page 200

Hi-Res – High-Resolution Extension 16.1 Features • Increases waveform generator resolution bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 16.2 Overview ...

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