ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 170

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.12.9
8291A–AVR–10/11
CTRLGCLR/CTRLGSET – Control register G Clear/Set
Table 13-8.
• Bit 1 – LUPD: Lock Update
When this bit is set, no update of the buffered registers is performed, even though an UPDATE
condition has occurred. Locking the update ensures that all buffers, including DTI buffers, are
valid before an update is performed.
This bit has no effect when input capture operation is enabled.
• Bit 0 – DIR: Counter Direction
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that
the counter is in the down-counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode or by event actions,
but this bit can also be changed from software.
Refer to
how to access this type of status register.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:1 – CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These
bits are automatically cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if
the corresponding CCxIF is cleared.
• Bit 0 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically
cleared on an UPDATE condition.
Bit
+0x0A/ +0x0B
Read/Write
Initial Value
CMD
00
01
10
11
”CTRLFCLR/CTRLFSET – Control register F Clear/Set” on page 169
Command selections
7
–
R
0
Group Configuration
RESTART
R
6
–
0
UPDATE
RESET
NONE
R
5
–
0
CCDBV
R/W
4
0
Command Action
None
Force update
Force restart
Force hard reset (ignored if T/C is not in OFFstate)
CCCBV
R/W
3
0
Atmel AVR XMEGA B
CCBBV
R/W
2
0
CCABV
R/W
1
0
PERBV
R/W
0
0
for information on
CTRLGCLR/SET
170