ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 102

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.7.2
8291A–AVR–10/11
PRPA/B – Power Reduction Port A/B Register
• Bit 7 – LCD: LCD Module
Setting this bit stops the clock to the LCD module. When the bit is cleared the peripheral should
be reinitialized to ensure proper operation.
• Bit 6 – USB: USB Module
Setting this bit stops the clock to the USB module. When this bit is cleared, the peripheral should
be reinitialized to ensure proper operation.
• Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 4 – AES: AES Module
Setting this bit stops the clock to the AES module. When this bit is cleared, the peripheral should
be reinitialized to ensure proper operation.
• Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 2 – RTC: Real-Time Counter
Setting this bit stops the clock to the real-time counter. When this bit is cleared, the peripheral
should be reinitialized to ensure proper operation.
• Bit 1 – EVSYS: Event System
Setting this stops the clock to the event system. When this bit is cleared, the module will con-
tinue as before it was stopped.
• Bit 0 – DMA: DMA Controller
Setting this bit stops the clock to the DMA controller. This bit can be set only if the DMA control-
ler is disabled.
Note:
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – ADC: Power Reduction ADC
Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped.
Bit
+0x01/+0x02
Read/Write
Initial Value
Disabling of analog modules stops the clock to the analog blocks themselves and not only the
interfaces.
R
7
0
R
6
0
R
5
0
R
4
0
3
R
0
Atmel AVR XMEGA B
R
2
0
ADC
R/W
1
0
R/W
AC
0
0
PRPA/B
102

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