ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 309

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.4.12
24.4.13
8291A–AVR–10/11
Segment and Common Buses Swapping
Port Mask
Figure 24-10. Analog Connections vs. Internal or External Bias Generation
Segment and/or common buses can be swapped (mirrored) to give more flexibility for LCD inter-
connects. The first segment (or common) terminal pin becomes the last one, and so on.
It is very useful in Chip on Glass (CoG), Chip on Film (CoF) or Chip on Board (CoB)
technologies.
SEGSWP bit and COMSWP bit in the CRTLA register control the order of the respective termi-
nal buses.
Note:
For LCD panels that do not use all the available segment terminals of the device, it is possible to
mask some of the unused pins. PMSK bit-field in the CTRLC register defines the number of seg-
ment terminals used in the application. Up to 16 unused segment terminal pins can be used as
standard GPIO pins. They are always placed at the end of the segment terminal bus. The 8 last
pins of this bus will become PG[0:7] - Port G - and the following 8 pins will become PM[0:7] -
Port M.
The GPIO functions on LCD pins are enabled if the corresponding segment terminal is masked
or if the LCD controller is disabled. A pure segment terminal - not shared with GPIO - is
grounded via a pull-down resistor if it is masked or if the LCD controller is disabled.
Note:
Notes :
1: These values are provided for design guidance only. They should be optimized for the application by the designer based on actual LCD specifications.
2: Bias generation can be provided by other sources of voltage than a division resistor.
ATxmegaB Device
Internal Generation
Static or 1/3 Bias
1. Refer to specific device datasheet for availability of this feature.
SEGSWP bit, which reverses the segment terminal indexing, will be active even if the LCD control-
ler is disabled (ENABLE bit in the CRTLA register) and will thus also modify the GPIO pin
mapping.
BIAS2
BIAS1
CAPH
VLCD
CAPL
GND
VCC
VCC
100 nF
100 nF
100 nF
100 nF
100 nF
(1)
(1)
(1)
(1)
(1)
ATxmegaB Device
External Generation
Static
BIAS2
BIAS1
CAPH
VLCD
CAPL
GND
VCC
Ext.V
VCC
LCD
Atmel AVR XMEGA B
ATxmegaB Device
External Generation (example)
1/3 Bias
BIAS2
BIAS1
CAPH
VLCD
CAPL
GND
VCC
Ext.V
VCC
LCD
(2)
(2)
(2)
(2)
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