ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 310
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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24.5
24.5.1
8291A–AVR–10/11
Register Description
CTRLA – Control Register A
Examples of a 40-segment LCD controller:
• Bit 7 – ENABLE: LCD Enable
Writing this bit to one enables the LCD. By writing it to zero, the LCD is turned “OFF” immedi-
ately. Turning the LCD “OFF” while driving a display, drives the output to ground to discharge
the display (apart from segment terminals which will be controlled by GPIO settings).
• Bit 6 – XBIAS: External Bias Generation
When this bit is set, the LCD buffers which drive the intermediate voltage levels are turned
“OFF”. When XBIAS is “OFF”, an external source for V
• Bit 5 – DATLCK: Data Register Lock
Writing this bit to one freezes the Shadow Display Memory. If the Display Memory is modified,
the Shadow Display Memory is locked and the display remains unchanged. When the bit is
cleared, the Shadow Display Memory is updated when a new frame starts (see
page
• Bit 4 – COMSWP: Common Terminal Bus Swap
Writing this bit to one inverts the order of the common terminal bus (COM[3:0]). The common
terminals disabled by DUTY[1:0] are also affected (see
Table 24-4.
Note:
Bit
+0x00
Read/Write
Initial Value
• If 30 segments are used:
• If 20 segments are used:
DUTY[1:0]
Segment terminals [39:32] = PG[0:7]
Segment terminals [31:30] = PM[0:1]
Segment terminals [29:0] = SEG[29:0] , LCD
Segment terminals [39:32] = PG[0:7]
Segment terminals [31:24] = PM[0:7]
Segment terminals [23:20] = GND (pull down)
Segment terminals [19:0] = SEG[19:0] , LCD
303).
00
01
10
11
1. Refer to specific device datasheet for availability of this feature.
–
LCD
ENABLE
R/W
Common Terminal Bus Reverse
7
0
Number of COM
XBIAS
R/W
6
0
4
1
2
3
DATLCK
R/W
5
0
COMSWP = 0
COM3,COM2,COM1,COM0
–, –, –, COM0
–, –, COM1, COM0
–, COM2, COM1, COM0
COMSWP
R/W
, Port G (GPIO functions)
, Port M (GPIO functions)
, Port G (GPIO functions)
, Port M (GPIO functions)
4
0
SEGSWP
(LCD functions)
(LCD functions)
R/W
3
0
(1)
Atmel AVR XMEGA B
LCD
Table 24-4 on page
is necessary.
CLRDT
R/W
2
0
COMSWP = 1
COM0,COM1,COM2,COM3
COM0, –, –, –
COM0, COM1, –, –
COM0, COM1, COM2, –
SEGON
R/W
1
0
310).
BLANK
R/W
Figure 24-2 on
0
0
CTRLA
310
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