ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 365

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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27.5.2
27.6
8291A–AVR–10/11
Data Registers
Scanning the PDI Pins
Two observe-only cells are inserted to make the combined RESET and PDI_CLK pin and the
PDI_DATA pin observable. Even though the PDI_DATA pin is bidirectional, it is only made
observable in order to avoid any extra logic on the PDI_DATA output path.
Figure 27-3. An observe-only input cell.
The supported data registers that can be connected between TDI and TDO are:
Figure 27-4. JTAG data register overview.
• Bypass register (Ref: register A in
• Device identification register (Ref: register C in
• Boundary scan chain (Ref: register D in
• PDICOM data register (Ref: register B in
From system
pin
D
D
D
D
D
D
D
D
D
I/O PORTS
D
PDI
D
JTAG
Figure 27-4 on page
0
1
Figure 27-4 on page
Figure 27-4 on page
A
B
C
Internal registers
B
C
Figure 27-4 on page
C
B
CTRL
TAP
Atmel AVR XMEGA B
C
D Q
365).
To next cell
365).
365)
to all TCK
registers
365).
To system
logic
TMS
TCK
TDO
TDI
365

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