ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 395

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.11.4
29.11.4.1
8291A–AVR–10/11
EEPROM Programming
Addressing the EEPROM
2.
3.
during self-programming.
The result will be available in the NVM DATA0 register. The CPU is halted during the complete
execution of the command.
The EEPROM can be read and written from application code in any part of the flash. Its is both
byte and page accessible. This means that either one byte or one page can be written to the
EEPROM at once. One byte is read from the EEPROM during a read.
The EEPROM can be accessed through the NVM controller (I/O mapped), similar to accessing
the flash program memory, or it can be memory mapped into the data memory space to be
accessed similar to SRAM.
When accessing the EEPROM through the NVM controller, the NVM address (ADDR) register is
used to address the EEPROM, while the NVM data (DATA) register is used to store or load
EEPROM data.
For EEPROM page programming, the ADDR register can be treated as having two sections.
The least-significant bits address the bytes within a page, while the most-significant bits address
the page within the EEPROM. This is shown in
the page (E2BYTE) is held by the bits [BYTEMSB:0] in the ADDR register. The remaining bits
[PAGEMSB:BYTEMSB+1] in the ADDR register hold the EEPROM page address (E2PAGE).
Together E2BYTE and E2PAGE hold an absolute address to a byte in the EEPROM. The size of
E2WORD and E2PAGE will depend on the page and flash size in the device. Refer to the device
datasheet for details on this.
Figure 29-2. I/O mapped EEPROM addressing.
Load the NVM CMD register with the read fuses command.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
E2PAGE
E2END
00
01
02
NVM ADDR
EEPROM MEMORY
BIT
PAGE
WITHIN THE EEPROM
P
PAGE ADDRESS
A
G
E
M
S
B
E2PAGE
Figure 29-2 on page
B
Y
T
E
M
E2BYTE
S
Atmel AVR XMEGA B
B
BYTE ADDRESS
WITHIN A PAGE
0
DATA BYTE
PAGE
395. The byte address in
E2BYTE
00
01
02
E2PAGEEND
395