ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 168

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.12.5
13.12.6
8291A–AVR–10/11
CTRLE – Control register E
INTCTRLA – Interrupt Enable register A
Table 13-6.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – BYTEM[1:0]: Byte Mode
These bits select the timer/counter operation mode according to
Table 13-7.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
BYTEM[1:0]
EVSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
10nn
11xx
00
01
10
11
Timer event source selection.
7
–
R
0
Clock select.
R
7
–
0
NORMAL
BYTEMODE
SPLITMODE
Group Configuration
Group Configuration
R
6
–
0
R
6
–
0
OFF
CHn
R
5
–
0
R
5
–
0
Timer/counter is set to normal mode (timer/counter type 0)
Upper byte of the counter (CNTH) will be set to zero after
each counter clock cycle
Timer/counter 0 is split into two 8-bit timer/counters
(timer/counter type 2)
Reserved
Description
Event Source
None
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Event channel n, n={0,...,3}
Reserved
R
4
–
0
R
4
–
0
R/W
3
–
R
0
3
ERRINTLVL[1:0]
0
Atmel AVR XMEGA B
R/W
R
2
–
0
2
0
Table 13-7 on page
R/W
R
1
0
1
OVFINTLVL[1:0]
0
BYTEM[1:0]
R/W
R/W
0
0
0
0
168.
INTCTRLA
CTRLE
168