ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 194

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.2
15.6.3
15.6.4
8291A–AVR–10/11
Fault Restore Modes
Change Protection
On-Chip Debug
How the AWeX and timer/counter return from the fault state to normal operation after a fault,
when the fault condition is no longer active, can be selected from one of two different modes:
When returning from a fault state the DIR[7:0] bits corresponding to the enabled DTI channels
are restored. OUTOVEN is unaffected by the fault except that writing to the register from soft-
ware is blocked.
The UPDATE condition used to restore normal operation is the same as the one in the
timer/counter.
To avoid unintentional changes in the fault protection setup, all the control registers in the AWeX
extension can be protected by writing the corresponding lock bit in the advanced waveform
extension lock register. For more details, refer to
”AWEXLOCK – Advanced Waveform Extension Lock register” on page
When the lock bit is set, control register A, the output override enable register, and the fault
detection event mask register cannot be changed.
To avoid unintentional changes in the fault event setup, it is possible to lock the event system
channel configuration by writing the corresponding event system lock register. For more details,
refer to
on page
When fault detection is enabled, an on-chip debug (OCD) system receives a break request from
the debugger, which will by default function as a fault source. When an OCD break request is
received, the AWeX and corresponding timer/counter will enter a fault state, and the specified
fault action will be performed.
After the OCD exits from the break condition, normal operation will be started again. In cycle-by-
cycle mode, the waveform output will start on the first UPDATE condition after exit from break,
while in latched mode, the fault condition flag must be cleared in software before the output will
be restored. This feature guarantees that the output waveform enters a safe state during a
break.
It is possible to disable this feature.
• In latched mode, the waveform output will remain in the fault state until the fault condition is
• In cycle-by-cycle mode the waveform output will remain in the fault state until the fault
no longer active and the fault detect flag has been cleared by software. When both of these
conditions are met, the waveform output will return to normal operation at the next UPDATE
condition.
condition is no longer active. When this condition is met, the waveform output will return to
normal operation at the next UPDATE condition.
”I/O Memory Protection” on page 25
48.
and
”EVSYSLOCK – Event System Lock register”
”I/O Memory Protection” on page 25
Atmel AVR XMEGA B
48.
and
194