ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 28

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.14.11
8291A–AVR–10/11
STATUS – Status Register
• Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in
grammable Multilevel Interrupt Controller” on page
triggered when the BUSY flag in the STATUS is set to zero. Thus, the interrupt should not be
enabled before triggering an NVM command, as the NVMBUSY flag will not be set before the
NVM command is triggered. The interrupt should be disabled in the interrupt handler.
• Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
rupt that will be triggered when the BUSY flag in the STATUS is set to zero. Thus, the interrupt
should not be enabled before triggering an NVM command, as the BUSY flag wont be set before
the NVM command is triggered. The interrupt should be disabled in the interrupt handler.
• Bit 7 – NVMBUSY: Nonvolatile Memory Busy
The NVMBUSY flag indicates if the NVM is being programmed. Once an operation is started,
this flag is set and remains set until the operation is completed. The NVMBUSY flag is automati-
cally cleared when the operation is finished.
• Bit 6 – FBUSY: Flash Busy
The FBUSY flag indicates if a flash programming operation is initiated. Once an operation is
started the FBUSY flag is set and the application section cannot be accessed. The FBUSY flag
is automatically cleared when the operation is finished.
• Bit 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – EELOAD: EEPROM Page Buffer Active Loading
The EELOAD flag indicates that the temporary EEPROM page buffer has been loaded with one
or more data bytes. It remains set until an EEPROM page write or a page buffer flush operation
is executed. For more details see
• Bit 0 – FLOAD: Flash Page Buffer Active Loading
The FLOAD flag indicates that the temporary flash page buffer has been loaded with one or
more data bytes. It remains set until an application boot page write page buffer flush operation is
executed. For more details see
Bit
+0x04
Read/Write
Initial Value
NVMBUSY
R
7
0
FBUSY
R
6
0
”Flash and EEPROM Programming Sequences” on page
”Flash and EEPROM Programming Sequences” on page
5
–
R
0
R
4
–
0
R
3
–
0
119. This is a level interrupt that will be
Atmel AVR XMEGA B
R
2
–
0
EELOAD
1
R
0
119. This is a level inter-
”Interrupts and Pro-
FLOAD
R
0
0
STATUS
386.
386.
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