ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 220

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.10 Interrupts and Events
8291A–AVR–10/11
Figure 18-10. Transfer complete FIFO.
To manage the FIFO, a five-bit write pointer (FIFOWP) and five-bit read pointer (FIFORP) are
used by the USB module and application software, respectively. FIFORP and FIFOWP are one's
complemented, and thus hold negative values. The SRAM location of the data is the sum of
EPPTR and the read or write pointer. The number of items in the FIFO is the difference between
FIFOWP and FIFORP. For the programmer, the FIFORP and FIFOWP values have to be cast to
a signed 8-bit integer, and then the offset into the FIFO from this signed integer must be
deducted.
The transaction complete interrupt flag (TRNIF) in the INFLAGSB[CLR,SET] register is set to
indicate a non-empty FIFO when FIFORP != FIFOWP, cleared when they are equal, and also
set when the FIFO is full.
Each time an endpoint IN or OUT transaction completes successfully, its endpoint configuration
table address is stored in the FIFO at the current write pointer position (i.e., EPPTR + 2 ×
FIFOWP) and FIFOWP is decremented. When the pointer reaches the FIFO size, it wraps to
zero. When application software reads FIFORP, this is decremented in the same way. Reading
the write pointer has no effect. The endpoint configuration table address can then be read
directly from (EPPTR + 2 × FIFORP).
Figure 18-11. USB transaction complete FIFO example.
The USB module can generate interrupts and events. The module has 10 interrupt sources.
These are split between two interrupt vectors, the transaction complete (TRNCOMPL) interrupt
and the bus event (BUSEVENT) interrupt. An interrupt group is enabled by setting its interrupt
level (INTLVL), while different interrupt sources are enabled individually or in groups.
FIFOWP
4x( MAXEP +1)
EPPTR –
ADDRESS
SRAM
EPPTR
FIFO
FIFOWP
FIFORP
FIFOWP
Ep X
USB_ TC_ FIFO
INTERNAL SRAM
ENDPOINT DESCRIPTOR TABLE
FIFO
X
FIFORP
FIFOWP
TC_ EP_ ADDRH _ MAX
EpY
TC_ EP_ ADDRH_2
TC_ EP_ ADDRH_2
TC_EP_ ADDRL_1
TC_ EP_ ADDRH_1
TC_EP_ ADDRL_0
TC _ EP _ ADDRH_0
Atmel AVR XMEGA B
FIFO
X
Y
FIFORP
FIFOWP
FIFOWP
Ep Z
FIFO
Y
Y
X
X
Z
Z
FIFORP
t
FIFORP
FIFORP
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