ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 314

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.5
24.5.6
8291A–AVR–10/11
INTFLAGS – Interrupt Flag Register
CTRLD – Control Register D
• Bits 7:3 – XIME[4:0]: eXtended Interrupt Mode Enable
XIME bit-field defines the number of frames to be completed for one interrupt period.
Note:
• Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 1:0 – FCINTLVL[1:0]: Interrupt Level
This bit-field enables the LCD frame completed interrupt and selects the interrupt level as
described in
enabled interrupt will be triggered when the FCIF flag in the INTFLAGS register is set.
• Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – FCIF: LCD Frames Completed Interrupt Flag
The generation of this flag depends on the XIME value in the INTCTRL register.
This bit is set by hardware at the beginning of a frame. FCIF is cleared by hardware when exe-
cuting the corresponding interrupt handling routine. Alternatively, writing a logical one to the flag
clears FCIF.
• Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
• For default waveforms, the FCIF flag is generated every XIME[4:0] + 1 frames. The range is 1
• For low power waveforms requiring 2 subsequent frames, the FCIF flag is generated every
up to 32 frames.
2 x ( XIME[4:0] + 1 ) frames. The range is 2 up to 64 frames.
This extended interrupt mode generates a stable time base from the frame rate.
”Interrupts and Programmable Multilevel Interrupt Controller” on page
R
R
7
–
0
7
–
0
Interrupt Period = ( ( XIME[4:0] + 1 ) x 2
6
–
R
0
6
–
R
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
BLINKEN
R/W
R
3
–
0
3
0
Atmel AVR XMEGA B
LPWAV
R
R
2
–
0
2
–
0
) frames
R/W
BLINKRATE[1:0]
1
–
R
0
1
0
FCIF
R/W
R/W
0
0
0
0
119. The
INTFLAGS
CTRLD
314