ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 376

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.5.1
28.5.2
28.5.3
28.5.4
8291A–AVR–10/11
Switching between PDI and JTAG modes
Accessing Internal Interfaces
NVM Programming Key
Exception Handling
The PDI controller uses either the JTAG or PDI physical layer for establishing a connection to
the programmer. Based on this, the PDI is in either JTAG or PDI mode. When one of the modes
is entered, the PDI controller registers will be initialized, and the correct clock source will be
selected. The PDI mode has higher priority than the JTAG mode. Hence, if the PDI mode is
enabled while the PDI controller is already in JTAG mode, the access layer will automatically
switch over to PDI mode. If switching physical layer without powering on/off the device, the
active layer should be disabled before the alternative physical layer is enabled.
After an external programmer has established communication with the PDI, the internal inter-
faces are not accessible, by default. To get access to the NVM controller and the nonvolatile
memories for programming, a unique key must be signaled by using the KEY instruction. The
internal interfaces are accessed as one linear address space using a dedicated bus (PDIBUS)
between the PDI and the internal interfaces. The PDIBUS address space is shown in
3 on page
the NVM interface. The PDI controller can access the NVM and NVM controller in programming
mode only. The PDI controller does not need to access the NVM controller's data or address
registers when reading or writing NVM.
The key that must be sent using the KEY instruction is 64 bits long. The key that will enable
NVM programming is:
0x1289AB45CDD888FF
There are several situations that are considered exceptions from normal operation. The excep-
tions depend on whether the PDI is in RX or TX mode and whether PDI or JTAG mode is used.
While the PDI is in RX mode, the exceptions are:
While the PDI is in TX mode, the exceptions are:
Exceptions are signaled to the PDI controller. All ongoing operations are then aborted, and the
PDI is put in ERROR state. The PDI will remain in ERROR state until a BREAK is sent from the
external programmer, and this will bring the PDI back to its default RX state.
• PDI:
• JTAG:
• PDI:
• JTAG:
– The physical layer detects a parity error
– The physical layer detects a frame error
– The physical layer recognizes a BREAK character (also detected as a frame error)
– The physical layer detects a parity error
– The physical layer recognizes a BREAK character (also detected as a parity error)
– The physical layer detects a data collision
– The physical layer detects a parity error (on the dummy data shifted in on TDI)
– The physical layer recognizes a BREAK character
444. The NVM controller must be enabled for the PDI controller to have any access to
Atmel AVR XMEGA B
Figure 33-
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