ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 257

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.3
8291A–AVR–10/11
STATUS – Status register
Table 19-8.
Writing the CMD bits will automatically clear the slave interrupt flags and CLKHOLD, and
release the SCL line. The ACKACT bit and CMD bits can be written at the same time, and then
the acknowledge action will be updated before the command is triggered.
• Bit 7
This fflag is set when a data byte is successfully received; i.e., no bus error or collision occurred
during the operation. Writing a one to this bit location will clear DIF. When this flag is set, the
slave forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will
release the SCL line.
This flag is also cleared automatically when writing a valid command to the CMD bits in the
CTRLB register
• Bit 6
This flag is set when the slave detects that a valid address has been received, or when a trans-
mit collision is detected. If the PIEN bit in the CTRLA register is set, a STOP condition on the
bus will also set APIF. Writing a one to this bit location will clear APIF. When set for an address
interrupt, the slave forces the SCL line low, stretching the TWI clock period. Clearing the inter-
rupt flags will release the SCL line.
The flag is also cleared automatically for the same condition as DIF.
• Bit 5
This flag is set when the slave is holding the SCL line low.This is a status flag and a read-only bit
that is set when DIF or APIF is set. Clearing the interrupt flags and releasing the SCL line will
indirectly clear this flag.
Bit
+0x02
Read/Write
Initial Value
CMD[1:0]
11
–
–
–
DIF: Data Interrupt Flag
APIF: Address/Stop Interrupt Flag
CLKHOLD: Clock Hold
R/W
DIF
7
0
TWI slave command. (Continued)
Configuration
RESPONSE
Group
APIF
R/W
6
0
CLKHOLD
R
5
0
Used in response to an address byte (APIF is set)
Used in response to a data byte (DIF is set)
DIR
0
1
0
1
RXACK
R
4
0
Operation
Execute acknowledge action succeeded by reception
of next byte
Execute acknowledge action succeeded by DIF
being set
Execute acknowledge action succeeded by waiting
for the next byte
No operation
COLL
R/W
3
0
Atmel AVR XMEGA B
BUSERR
R/W
2
0
R/W
DIR
1
0
R/W
AP
0
0
STATUS
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