ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 369

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.3.1
28.3.2
28.3.3
8291A–AVR–10/11
Enabling
Disabling
Frame Format and Characters
The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA
line high for a period longer than the equivalent external reset minimum pulse width (refer to
device datasheet for external reset pulse width data). This will disable the RESET functionality of
the Reset pin, if not already disabled by the fuse settings.
Next, continue to keep the PDI_DATA line high for 16 PDI_CLK cycles. The first PDI_CLK cycle
must start no later than 100µs after the RESET functionality of the Reset pin is disabled. If this
does not occur in time, the enabling procedure must start over again. The enable sequence is
shown in
Figure 28-3. PDI physical layer enable sequence.
The Reset pin is sampled when the PDI interface is enabled. The reset register is then set
according to the state of the Reset pin, preventing the device from running code after the reset
functionality of this pin is disabled.
If the clock frequency on PDI_CLK is lower than approximately 10kHz, this is regarded as inac-
tivity on the clock line. This will automatically disable the PDI. If not disabled by a fuse, the reset
function of the Reset (PDI_CLK) pin is enabled again. This also means that the minimum pro-
gramming frequency is approximately 10kHz.
The PDI physical layer uses a frame format defined as one character of eight data bits, with a
start bit, a parity bit, and two stop bits.
Figure 28-4. PDI serial frame format.
PDI_DATA
PDI_CLK
St
(0-7)
P
Sp1
Sp2
(IDLE)
Start bit, always low
Data bits (0 to 7)
Parity bit, even parity used
Stop bit 1, always high
Stop bit 2, always high
Figure 28-3 on page
St
Disable RESET function on Reset (PDI_CLK) pin
0
1
369.
2
3
FRAME
4
5
6
Atmel AVR XMEGA B
7
P
Sp1
Activate PDI
Sp2
(St/IDLE)
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