ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 400

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.12.3
8291A–AVR–10/11
CMD[6:0]
Flash Page Buffer
Flash
Application Section
0x2B
0x2E
0x2F
0x00
0x40
0x43
0x23
0x26
0x78
0x20
0x22
0x24
0x25
NVM Commands
Commands / Operation
No operation
Chip erase
Read NVM
Load flash page buffer
Erase flash page buffer
Erase flash page
Write flash page
Erase and write flash page
Flash CRC
Erase application section
Erase application section page
Write application section page
Erase and write application section page
(1)
data registers, but the NVM controller must be loaded with the correct command (i.e., to read
from any NVM, the controller must be loaded with the NVM read command before loading data
from the PDIBUS address space). For the reminder of this section, all references to reading and
writing data or program memory addresses from the PDI refer to the memory map shown in
ure 29-3 on page
The PDI uses byte addressing, and hence all memory addresses must be byte addresses.
When filling the flash or EEPROM page buffers, only the least-significant bits of the address are
used to determine locations within the page buffer. Still, the complete memory mapped address
for the flash or EEPROM page is required to ensure correct address mapping.
During programming (page erase and page write) when the NVM is busy, the NVM is blocked for
reading.
The NVM commands that can be used for accessing the NVM memories from external program-
ming are listed in
programming.
For external programming, the trigger for action-triggered commands is to set the CMDEX bit in
the NVM CTRLA register (CMDEX). The read-triggered commands are triggered by a direct or
indirect load instruction (LDS or LD) from the PDI (PDI read). The write-triggered commands are
triggered by a direct or indirect store instruction (STS or ST) from the PDI (PDI write).
”Chip Erase” on page 401
rithm for each NVM operation. The commands are protected by the lock bits, and if read and
write lock is set, only the chip erase and flash CRC commands are available.
Table 29-5.
NVM commands available for external programming.
Table 29-5 on page
399.
through
”Write Fuse/ Lock Bit” on page 403
400. This is a superset of the commands available for self-
Atmel AVR XMEGA B
Trigger
-
CMDEX
PDI Read
PDI Write
CMDEX
PDI write
PDI write
PDI write
CMDEX
PDI write
PDI write
PDI write
PDI write
explain in detail the algo-
Change
Protected
Y
N
N
Y
N
N
N
Y
N
N
N
N
-
NVM Busy
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Fig-
400