ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 91

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.10.4
8291A–AVR–10/11
XOSCFAIL – XOSC Failure Detection Register
tor is selected as the source for the system clock, see
This configuration cannot be changed.
Table 7-8.
Notes:
• Bit 7:4 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to
this location will clear PLLFDIF.
• Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when
PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to
Change Protection” on page 12
• Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure
is detected. Writing logic one to this location will clear XOSCFDIF.
• Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be
issued when XOSCFDIF is set.
Bit
+0x03
Read/Write
Initial Value
XOSCSEL[4:0]
x
x
x
nnn
00000
00010
(4)
(4)
(4)
1. This option should be used only when frequency stability at startup is not important for the
2. This option is intended for use with ceramic resonators. It can also be used when the fre-
3. When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ
4. When the 0.4 - 16 MHz Crystal Oscillatoris selected, the MSB is then XOSCPWR.
0011
0111
1011
01
application. The option is not suitable for crystals.
quency stability at startup is not important for the application.
can be selected.
7
–
R
0
External oscillator selection and start-up time.
Group Configuration
R
6
–
0
XTAL_256CLK
XTAL_1KCLK
XTAL_16KCLK
EXTCLK_Cn
EXTCLK
32KHZ
for details.
R
5
–
0
(3)
(3)
(3)
(2)
(1)
4
–
R
0
External Clock from Port C pin n
External Clock from XTAL1 pin
PLLFDIF
Selected Clock Source
R/W
0.4MHz - 16MHz XTAL
0.4MHz - 16MHz XTAL
0.4MHz - 16MHz XTAL
3
0
32.768kHz TOSC
Atmel AVR XMEGA B
”CTRL – Control Register” on page
PLLFDEN
R/W
2
0
XOSCFDIF
R/W
1
0
XOSCFDEN
R/W
Start-up Time
0
0
”Configuration
16K CLK
256 CLK
16K CLK
1K CLK
6 CLK
6 CLK
XOSCFAIL
89.
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