ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 76

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. System Clock and Clock Options
7.1
7.2
8291A–AVR–10/11
Features
Overview
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XMEGA devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator sup-
port. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a
wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for
automatic run-time calibration of the internal oscillators to remove frequency drift over voltage
and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt
and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled.
After reset, the device will always start up running from the 2MHz internal oscillator. During nor-
mal operation, the system clock source and prescalers can be changed from software at any
time.
Figure 7-1 on page 77
all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be
stopped using sleep modes and power reduction registers, as described in
and Sleep Modes” on page
Fast start-up time
Safe run-time clock switching
Internal oscillators:
External clock options
PLL with 20MHz - 128MHz output frequency
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at 2 and 4 times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
– 32MHz run-time calibrated oscillator
– 2MHz run-time calibrated oscillator
– 32.768kHz calibrated oscillator
– 32kHz ultra low power (ULP) oscillator with 1kHz output
– 0.4MHz - 16MHz crystal oscillator
– 32.768kHz crystal oscillator
– External clock
– Internal and external clock options and 1x to 31x multiplication
– Lock detector
presents the principal clock system in the XMEGA family of devices. Not
97.
Atmel AVR XMEGA B
”Power Management
76