ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 125

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.7
11.8
11.8.1
8291A–AVR–10/11
Interrupt vector locations
Register Description
STATUS – Status register
Table 11-2 on page 125
tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This
is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in
the Boot section or vice versa.
Table 11-2.
• Bit 7 – NMIEX: Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning
(RETI) from the interrupt handler.
• Bit 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been
interrupted by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
• Bit 1 – MEDLVLEX: Medium-level Interrupt Executing
This flag is set when a medium-level interrupt is executing or when the interrupt handler has
been interrupted by an interrupt from higher level or an NMI. The flag will be cleared when
returning (RETI) from the interrupt handler.
• Bit 0 – LOLVLEX: Low-level Interrupt Executing
This flag is set when a low-level interrupt is executing or when the interrupt handler has been
interrupted by an interrupt from higher level or an NMI. The flag will be cleared when returning
(RETI) from the interrupt handler.
Bit
+0x00
Read/Write
Initial Value
BOOTRST
1
1
0
0
NMIEX
Reset and Interrupt vectors placement
R
7
0
IVSEL
0
1
0
1
R
6
–
0
shows reset and Interrupt vectors placement for the various combina-
Reset Address
0x0000
0x0000
Boot Reset Address
Boot Reset Address
R
5
–
0
R
4
–
0
R
3
–
0
Atmel AVR XMEGA B
HILVLEX
Interrupt Vectors Start Address
0x0002
Boot Reset Address + 0x0002
0x0002
Boot Reset Address + 0x0002
R
2
0
MEDLVLEX
R
1
0
LOLVLEX
R
0
0
STATUS
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