ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 44

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.18.7
4.18.8
8291A–AVR–10/11
ANAINIT – Analog Initialization Register
EVSYSLOCK – Event System Lock Register
• Bit 0 – JTAGD: JTAG Disable
Setting this bit will disable the JTAG interface. This bit is protected by the configuration change
protection mechanism or details refer to
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 / 1:0 – STARTUPDLYx
Setting these bits enables sequential start of internal components used for the ADC, DAC, and
analog comparator with main input/output connected to that port. When this is done, the internal
components such as voltage reference and bias currents are started sequentially when the mod-
ule is enabled. This reduces the peak current consumption during startup of the module. For
maximum effect the start-up delay should be set so that it is larger than 0.5µs.
Table 4-13.
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – EVSYS0LOCK:
Setting this bit will lock all registers in the event system related to event channels 0 to 3 for fur-
ther modification. The following registers in the event system are locked: CH0MUX, CH0CTRL,
CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, CH3CTRL. This bit is protected by the
configuration change protection mechanism or details refer to
on page
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
STARTUPDLYx
00
11
10
11
12.
Analog startup delay.
R
7
–
0
R
7
–
0
Group Configuration
R
6
–
0
R
6
–
0
32CLK
NONE
2CLK
8CLK
R
5
–
0
R
5
–
0
”Configuration Change Protection” on page
R
4
–
0
R
4
–
0
Description
Direct startup
2 * CLK
8 * CLK
32 * CLK
3
–
R
0
STARTUPDLYB[1:0]
PER
PER
R/W
PER
3
0
Atmel AVR XMEGA B
R
2
–
0
R/W
2
0
”Configuration Change Protection”
R
1
–
0
STARTUPDLYA[1:0]
R/W
1
0
EVSYS0LOCK
R/W
0
0
R/W
0
0
12.
EVSYSLOCK
ANAINIT
44