ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 343

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.16.2
8291A–AVR–10/11
MUXCTRL – MUX Control registers
• Bit 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:2 – GAIN[2:0]: Gain Factor
These bits define the gain factor for the ADC gain stage.
See
MUX Control registers” on page
Table 25-7.
• Bit 1:0 – INPUTMODE[1:0]: Channel Input Mode
These bits define the channel mode. Changing input mode will corrupt any data in the pipeline.
Table 25-8.
Table 25-9.
The MUXCTRL register defines the input source for the channel.
Bit
+0x01
Read/Write
Initial Value
INPUTMODE[1:0]
INPUTMODE[1:0]
Table 25-5 on page
00
01
10
11
00
01
10
11
GAIN[2:0]
000
001
010
011
100
101
110
111
ADC gain factor.
Channel input modes, CONVMODE=0 (unsigned mode).
Channel input modes, CONVMODE=1 (signed mode).
R
7
–
0
Group Configuration
INTERNAL
SINGLEENDED
DIFF
DIFFWGAIN
INTERNAL
SINGLEENDED
R/W
339. Gain is valid only with certain MUX settings. See
6
0
Group Configuration
343.
R/W
5
0
MUXPOS[3:0]
Group Configuration
R/W
4
0
DIV2
16X
32X
64X
1X
2X
4X
8X
R/W
Description
Internal positive input signal
Single-ended positive input signal
Differential input signal
Differential input signal with gain
Description
Internal positive input signal
Single-ended positive input signal
Reserved
Reserved
3
0
Atmel AVR XMEGA B
R
2
0
MUXNEG[2:0]
R/W
1
0
Gain Factor
16x
32x
64x
½x
1x
2x
4x
8x
R/W
0
0
”MUXCTRL –
MUXCTRL
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