ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 277

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.8.2
21.8.3
8291A–AVR–10/11
Asynchronous Data Recovery
Asynchronous Operational Range
The data recovery unit uses sixteen samples in normal mode and eight samples in double speed
mode for each bit.
Figure 21-7. Sampling of data and parity bits.
As for start bit detection, an identical majority voting technique is used on the three center sam-
ples for deciding of the logic level of the received bit. The process is repeated for each bit until a
complete frame is received. It includes the first stop bit, but excludes additional ones. If the sam-
pled stop bit is a 0 value, the frame error (FERR) flag will be set.
Figure 21-8 on page 277
beginning of the next frame's start bit.
Figure 21-8. Stop bit and next start bit sampling.
A new high-to-low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For normal speed mode, the first low level sample can be at the
point marked (A) in Stop Bit Sampling and Next Start Bit Sampling. For double speed mode, the
first low level must be delayed to point (B). Point (C) marks a stop bit of full length at nominal
baud rate. The early start bit detection influences the operational range of the receiver.
The operational range of the receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If an external transmitter is sending using bit rates
that are too fast or too slow, or if the internally generated baud rate of the receiver does not
match the external source’s base frequency, the receiver will not be able to synchronize the
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
(CLK2X = 0)
(CLK2X = 1)
(CLK2X = 0)
(CLK2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
Figure 21-7 on page 277
1
1
1
1
2
2
shows the sampling of the stop bit in relation to the earliest possible
3
2
3
2
4
4
5
3
5
3
6
6
shows the sampling process of data and parity bits.
7
4
7
4
8
8
STOP 1
BIT n
9
5
9
5
Atmel AVR XMEGA B
10
10
(A)
0/1
11
6
6
0/1
12
(B)
0/1
0/1
13
7
14
15
8
16
(C)
1
1
277