ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 275

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.6.1
21.6.2
21.7
21.7.1
21.7.2
8291A–AVR–10/11
Data Reception - The USART Receiver
Sending Frames
Disabling the Transmitter
Receiving Frames
Receiver Error Flags
A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent.
The data in the transmit buffer are moved to the shift register when the shift register is empty
and ready to send a new frame. The shift register is loaded if it is in idle state (no ongoing trans-
mission) or immediately after the last stop bit of the previous frame is transmitted. When the shift
register is loaded with data, it will transfer one complete frame.
The transmit complete interrupt flag (TXCIF) is set and the optional interrupt is generated when
the entire frame in the shift register has been shifted out and there are no new data present in
the transmit buffer.
The transmit data register (DATA) can only be written when the data register empty flag (DREIF)
is set, indicating that the register is empty and ready for new data.
When using frames with fewer than eight bits, the most-significant bits written to DATA are
ignored. If 9-bit characters are used, the ninth bit must be written to the TXB8 bit before the low
byte of the character is written to DATA.
A disabling of the transmitter will not become effective until ongoing and pending transmissions
are completed; i.e., when the transmit shift register and transmit buffer register do not contain
data to be transmitted. When the transmitter is disabled, it will no longer override the TxDn pin,
and the pin direction is set as input automatically by hardware, even if it was configured as out-
put by the user.
When the receiver is enabled, the RxD pin functions as the receiver's serial input. The direction
of the pin must be set as input, which is the default pin setting.
The receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCK clock and shifted into the receive shift register until
the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When
the first stop bit is received and a complete serial frame is present in the receive shift register,
the contents of the shift register will be moved into the receive buffer. The receive complete
interrupt flag (RXCIF) is set, and the optional interrupt is generated.
The receiver buffer can be read by reading the data register (DATA) location. DATA should not
be read unless the receive complete interrupt flag is set. When using frames with fewer than
eight bits, the unused most-significant bits are read as zero. If 9-bit characters are used, the
ninth bit must be read from the RXB8 bit before the low byte of the character is read from DATA.
The USART receiver has three error flags. The frame error (FERR), buffer overflow (BUFOVF)
and parity error (PERR) flags are accessible from the status register. The error flags are located
in the receive FIFO buffer together with their corresponding frame. Due to the buffering of the
error flags, the status register must be read before the receive buffer (DATA), since reading the
DATA location changes the FIFO buffer.
Atmel AVR XMEGA B
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