ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 68

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.5
6.6
8291A–AVR–10/11
Event Timing
Filtering
Figure 6-3.
Four multiplexers means that it is possible to route up to four events at the same time. It is also
possible to route one event through several multiplexers.
Not all XMEGA devices contain all peripherals. This only means that a peripheral is not available
for generating or using events. The network configuration itself is compatible between all
devices.
An event normally lasts for one peripheral clock cycle, but some event sources, such as a low
level on an I/O pin, will generate events continuously. Details on this are described in the
datasheet for each peripheral, but unless otherwise stated, an event lasts for one peripheral
clock cycle.
It takes a maximum of two peripheral clock cycles from when an event is generated until the
event actions in other peripherals are triggered. This ensures short and 100% predictable
response times, independent of CPU or DMA controller load or software revisions.
Each event channel includes a digital filter. When this is enabled, an event must be sampled
with the same value for a configurable number of system clock cycles before it is accepted. This
is primarily intended for pin change events.
(4)
(4)
(4)
(4)
Event routing network.
PORTA
PORTD
PORTB
PORTC
PORTE
Clk
ADCA
ADCB
TCC0
TCC1
TCE0
USB
ACA
ACB
RTC
PER
(16)
(4)
(3)
(3)
(2)
(6)
(4)
(1)
(1)
(8)
(8)
(8)
(3)
(8)
Event Channel 3
Event Channel 2
Event Channel 1
Event Channel 0
(35)
(10)
(30)
(6)
Atmel AVR XMEGA B
CH0CTRL[7:0]
CH1CTRL[7:0]
CH2CTRL[7:0]
CH3CTRL[7:0]
CH0MUX[7:0]
CH1MUX[7:0]
CH2MUX[7:0]
CH3MUX[7:0]
68