ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 178

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5
14.5.1
8291A–AVR–10/11
Counter Operation
Changing the Period
Figure 14-2. Clock selection.
The peripheral clock (clk
a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the
whole range of time prescalings from 1 to 2
The clock selection (CLKSEL) selects one of the clock prescaler outputs or an event channel for
the high-byte counter (HCNT) and low-byte counter (LCNT). By using the event system, any
event source, such as an external clock signal, on any I/O pin can be used as the clock input.
By default, no clock input is selected, and the counters are not running.
The counters will always count in single-slope mode. Each counter counts down for each clock
cycle until it reaches BOTTOM, and then reloads the counter with the period register value at the
following clock cycle.
Figure 14-3. Counter operation.
As shown in
access has higher priority than the count clear, and reloads and will be immediate.
The counter period is changed by writing a new TOP value to the period register. Since the
counter is counting down, the period register can be written at any time without affecting the cur-
rent period, as shown in
odd waveforms.
CNT
BOTTOM
clk
Figure
MAX
TOP
PER
CLKSEL
14-3, the counter can change the counter value while running. The write
Prescaler
Common
PER
Figure 14-4 on page
) is fed into the common prescaler (common for all timer/counters in
{1,2,4,8,64,256,1024}
clk
PER
/
clk
15
2
{0,...,15}
CNT written
PER
is available through the event system.
179. This prevents wraparound and generation of
/
event channels
Atmel AVR XMEGA B
System
Event
CNT
events
"reload"
178