ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 361

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8291A–AVR–10/11
The IEEE Std. 1149.1-2001 also specifies an optional test reset signal, TRST. This signal is not
available.
When the JTAGEN fuse is unprogrammed or the JTAG disable bit is set, the JTAG interface is
disabled. The four TAP pins are normal port pins, and the TAP controller is in reset. When
enabled, the input TAP signals are internally pulled high and JTAG is enabled for boundary scan
operations.
Figure 27-1. TAP controller state diagram.
The TAP controller is a 16-state, finite state machine that controls the operation of the boundary
scan circuitry. The state transitions shown in
(shown adjacent to each state transition) at the time of the rising edge on TCK. The initial state
after a power-on reset is the test logic reset state.
Assuming the present state is run test/idle, a typical scenario for using the JTAG interface is:
• TDI: Test data in. Serial input data to be shifted in to the instruction register or data register
• TDO: Test data out. Serial output data from the instruction register or data register
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the shift
(scan chains)
instruction register, or shift IR, state. While in this state, shift the four bits of the JTAG
instruction into the JTAG instruction register from the TDI input at the rising edge of TCK. The
TMS input must be held low during input of the 3 lsbs in order to remain in the shift IR state.
The msb of the instruction is shifted in when this state is left by setting TMS high. While the
instruction is shifted in from the TDI pin, the captured IR state, 0x01, is shifted out on the
Figure 27-1
Atmel AVR XMEGA B
depend on the signal present on TMS
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