ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 375

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.4.7
28.5
8291A–AVR–10/11
PDI Controller
Serial Reception
If the PDI is in TX- mode (as a response to an LD instruction), but no transmission request from
the PDI controller is pending when the TAP controller enters the capture DR state, a DELAY
byte (0xDB) will be loaded into the shift register, and the parity bit will be set (forcing a parity
error) when data is shifted out in the shift DR state. This situation occurs during data transmis-
sion if the data to be transmitted is not yet available.
Figure 28-13 on page 375
response to the repeated indirect LD instruction. In this example, the device is not able to return
data bytes faster than one valid byte per two transmitted frames. Thus, intermediate DELAY
characters are inserted.
Figure 28-13. Data not ready marking.
If a DELAY data frame is transmitted as a response to an LD instruction, the programmer should
interpret this as if the JTAG interface had no data ready for transmission in the previous capture
DR state. The programmer must initiate repeated transfers until a valid data byte is received.
The LD instruction is defined to return a specified number of valid frames, not just a number of
frames. Hence, if the programmer detects a DELAY character after transmitting an LD instruc-
tion, the LD instruction should not be retransmitted, because the first LD response would still be
pending.
During reception, the PDI collects the eight data bits and the parity bit from TDI and shifts them
into the shift register. Every time a valid frame is received, the data is latched in to the update
DR state.
The parity checker calculates the parity (even mode) of the data bits in incoming frames and
compares the result with the parity bit from the serial frame. In case of a parity error, the PDI
controller is signaled.
The parity checker is active in both TX and RXmodes. If a parity error is detected, the received
data byte is evaluated and compared with the BREAK character (which will always generate a
parity error). In case the BREAK character is recognized, the PDI controller is signaled.
The PDI controller performs data transmission/reception on a byte level, command decoding,
high-level direction control, control and status register access, exception handling, and clock
switching (PDI_CLK or TCK). The interaction between an external programmer and the PDI con-
troller is based on a scheme where the programmer transmits various types of requests to the
PDI controller, which in turn responds according to the specific request. A programmer request
comes in the form of an instruction, which may be followed by one or more byte operands. The
PDI controller response may be silent (e.g., a data byte is stored to a location within the device),
or it may involve data being returned to the programmer (e.g., a data byte is read from a location
within the device).
Programmer
External
Commands/data
Device
FRAME 0
REP
shows an uninterrupted flow of data frames from the PDI as a
FRAME 1
CNT
LD *(ptr)
FRAME 2
Atmel AVR XMEGA B
0xDB 1
FRAME 0
FRAME 1
D0
P 0xDB 1
FRAME 2
FRAME 3
D1
P
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