ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 161
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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13.8.2
13.8.3
8291A–AVR–10/11
Frequency (FRQ) Waveform Generation
Single-slope PWM Generation
Inverted waveform output is achieved by setting the invert output bit for the port pin.
For frequency generation the period time (T) is controlled by the CCA register instead of PER.
The waveform generation (WG) output is toggled on each compare match between the CNT and
CCA registers, as shown in
Figure 13-14. Frequency waveform generation.
The waveform frequency (f
where N represents the prescaler divider used. The waveform generated will have a maximum
frequency of half of the peripheral clock frequency (fclk
and no prescaling is used. This also applies when using the hi-res extension, since this
increases the resolution and not the frequency.
For single-slope PWM generation, the period (T) is controlled by PER, while CCx registers con-
trol the duty cycle of the WG output.
to TOP and then restarts from BOTTOM. The waveform generator (WG) output is set on the
compare match between the CNT and CCx registers and cleared at TOP.
f
FRQ
3. The CC channels used must be enabled. This will override the corresponding port pin
4. The direction for the associated port pin must be set to output.
CNT
WG Output
output register.
=
---------------------------------- -
2N CCA
BOTTOM
fclk
(
MAX
TOP
PER
+
1
)
FRQ
Figure 13-14 on page
Period (T)
) is defined by the following equation:
Figure 13-15
Direction Change
shows how the counter counts from BOTTOM
161.
Atmel AVR XMEGA B
PER
) when CCA is set to zero (0x0000)
CNT written
"update"
161
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