ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 377

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.5.5
28.5.6
28.5.6.1
28.5.6.2
28.5.6.3
28.5.6.4
8291A–AVR–10/11
Reset Signalling
Instruction Set
LDS - Load Data from PDIBUS Data Space using Direct Addressing
STS - Store Data to PDIBUS Data Space using Direct Addressing
LD - Load Data from PDIBUS Data Space using Indirect Addressing
ST - Store Data to PDIBUS Data Space using Indirect Addressing
Due to this mechanism, the programmer can always synchronize the protocol by transmitting
two successive BREAK characters.
Through the reset register, the programmer can issue a reset and force the device into reset.
After clearing the reset register, reset is released, unless some other reset source is active.
The PDI has a small instruction set used for accessing both the PDI itself and the internal inter-
faces. All instructions are byte instructions. The instructions allow an external programmer to
access the PDI controller, the NVM controller and the nonvolatile memories.
The LDS instruction is used to load data from the PDIBUS data space for read out. The LDS
instruction is based on direct addressing, which means that the address must be given as an
argument to the instruction. Even though the protocol is based on byte-wise communication, the
LDS instruction supports multiple-byte addresses and data access. Four different address/data
sizes are supported: single-byte, word (two bytes), three-byte, and long (four bytes). Multiple-
byte access is broken down internally into repeated single-byte accesses, but this reduces pro-
tocol overhead. When using the LDS instruction, the address byte(s) must be transmitted before
the data transfer.
The STS instruction is used to store data that are serially shifted into the physical layer shift reg-
ister to locations within the PDIBUS data space. The STS instruction is based on direct
addressing, which means that the address must be given as an argument to the instruction.
Even though the protocol is based on byte-wise communication, the ST instruction supports
multiple-bytes addresses and data access. Four different address/data sizes are supported: sin-
gle-byte, word (two bytes), three-byte, and long (four bytes). Multiple-byte access is broken
down internally into repeated single-byte accesses, but this reduces protocol overhead. When
using the STS instruction, the address byte(s) must be transmitted before the data transfer.
The LD instruction is used to load data from the PDIBUS data space into the physical layer shift
register for serial read out. The LD instruction is based on indirect addressing (pointer access),
which means that the address must be stored in the pointer register prior to the data access.
Indirect addressing can be combined with pointer increment. In addition to reading data from the
PDIBUS data space, the LD instruction can read the pointer register. Even though the protocol is
based on byte-wise communication, the LD instruction supports multiple-byte addresses and
data access. Four different address/data sizes are supported: single-byte, word (two bytes),
three-byte, and long (four bytes). Multiple-byte access is broken down internally into repeated
single-byte accesses, but this reduces the protocol overhead.
The ST instruction is used to store data that is serially shifted into the physical layer shift register
to locations within the PDIBUS data space. The ST instruction is based on indirect addressing
(pointer access), which means that the address must be stored in the pointer register prior to the
data access. Indirect addressing can be combined with pointer increment. In addition to writing
data to the PDIBUS data space, the ST instruction can write the pointer register. Even though
the protocol is based on byte-wise communication, the ST instruction supports multiple-bytes
Atmel AVR XMEGA B
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