ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 180
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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14.6.3
14.7
8291A–AVR–10/11
Interrupts and Events
Port Override for Waveform Generation
The PER register defines the PWM resolution. The minimum resolution is two bits
(PER=0x0003), and the maximum resolution is eight bits (PER=MAX).
The following equation is used to calculate the exact resolution for a single-slope PWM
(R
The single, slow PWM frequency (f
eral clock frequency (f
where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).
To make the waveform generation available on the port pins, the corresponding port pin direc-
tion must be set as output. The timer/counter will override the port pin values when the CMP
channel is enabled (LCMPENx/HCMPENx).
Figure 14-6 on page 180
the low-byte timer/counter, CMP channels A to D will override the output value (OUTxn) of port
pins 0 to 3 on the corresponding port pins (Pxn). For the high-byte timer/counter, CMP channels
E to H will override port pins 4 to 7. Enabling inverted I/O on the port pin (INVENxn) inverts the
corresponding WG output.
Figure 14-6. Port override for low- and high-byte timer/counters.
The timer/counters can generate interrupts and events. The counter can generate an interrupt
on underflow, and each CMP channel for the low-byte counter has a separate compare interrupt.
Events will be generated for all conditions that can generate interrupts. For details on event gen-
eration and available events, refer to
f
R
PWM_SS
PWM_SS
PWM_SS
) waveform:
=
=
------------------------------ -
N PER
log
---------------------------------- -
(
f
(
log
PER
PER
Waveform
2 ( )
+
1
+
)
PER
1
)
), and it is calculated by using the following equation:
shows the port override for the low- and high-byte timer/counters. For
LCMPENx /
HCMPENx
PWM_SS
”Event System” on page
) depends on the period setting (PER) and the periph-
OUT
Atmel AVR XMEGA B
INVEN
70.
OCx
180
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