ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 23

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.9
4.9.1
4.10
8291A–AVR–10/11
Data Memory and Bus Arbitration
Memory Timing
Bus Priority
Since the data memory is organized as four separate sets of memories, the different bus mas-
ters (CPU, DMA controller read and DMA controller write, etc.) can access different memories at
the same time. As
while the DMA controller is transferring data from internal SRAM to I/O memory. The USB mod-
ule acts as a bus master and is connected directly to internal SRAM through a pseudo-dualport
(PDP) interface.
Figure 4-3.
When several masters request access to the same bus, the bus priority is in the following order
(from higher to lower priority):
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and read from SRAM takes two cycles. For burst read (DMA), new data available
every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read.
For burst read, new data are available every second cycle. Refer to the instruction summary for
more details on instructions and instruction timing.
1. Bus Master with ongoing access.
2. Bus Master with ongoing burst.
3. Bus Master requesting burst access.
4. Bus Master requesting bus access.
a. Alternating DMA controller read and DMA controller write when they access the
a. CPU has priority.
a. CPU has priority.
same data memory section.
Bus access.
Figure 4-3 on page 23
Non-Volatile
EEPROM
Memory
Flash
CH0
DMA
CH1
Management
Peripherals and system modules
Modules
Crypto
Power
ADC
AC
CRC
AVR core
shows, the CPU can access the EEPROM memory
Bus matrix
USART
System
LCD
Event
CPU
TWI
SPI
OCD
Real Time
Controller
Oscillator
Atmel AVR XMEGA B
Interrupt
Counter
Counter
Control
Timer /
USB
I/O
Programming
External
PDI
SRAM
RAM
23