ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 61

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.5
8291A–AVR–10/11
TRFCNTL – Block Transfer Count Register L
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Note:
Table 5-13.
The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1
CC channel A the transfer trigger.
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT
defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each
TRGSRC Offset Value
TRGSRC Offset Value
TRGSRC Offset Value
TRIGSRC Base Value
TRGSRC offset value
1. CC channel C and D triggers are available only for Timer/Counters 0.
+0x00
+0x01
+0x02
+0x00
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
0x4B
0x8B
0x80
0x00
0x01
DMA trigger source base values for all modules and peripherals. (Continued)
DMA trigger source offset values for event system triggers.
DMA trigger source offset values for ADC triggers.
DMA trigger source offset values for timer/ counter triggers.
DMA trigger source offset values for USART triggers.
Group Configuration
Group Configuration
Group Configuration
Group Configuration
Group Configuration
USARTC0
USARTE0
CCC
CCD
TCE0
ERR
CCA
CCB
RXC
DRE
CH0
CH1
CH2
CH0
OVF
(1)
(1)
Description
USART C0 DMA triggers base value
Timer/counter E0 DMA triggers base value
USART E0 DMA triggers base value
Description
Event channel 0
Event channel 1
Event channel 2
Description
ADC channel
Description
Overflow/underflow
Error
Compare or capture channel A
Compare or capture channel B
Compare or capture channel C
Compare or capture channel D
Description
Receive complete
Data register empty
Atmel AVR XMEGA B
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