ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 184

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.10.6
14.10.7
8291A–AVR–10/11
INTCTRLB — Interrupt Enable register B
CTRLF — Control register F
• Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level
These bits enable the high-byte timer underflow interrupt and select the interrupt level, as
described in
enabled interrupt will be triggered when HUNFIF in the INTFLAGS register is set.
• Bit 1:0 – LUNFINTLVL[1:0]: Low-byte Timer Underflow Interrupt Level
These bits enable the low-byte timer underflow interrupt and select the interrupt level, as
described in
enabled interrupt will be triggered when LUNFIF in the INTFLAGS register is set.
• Bit 7:0 – LCMPxINTLVL[1:0]: Low-byte Compare x Interrupt Level
These bits enable the low-byte timer compare interrupt and select the interrupt level, as
described in
enabled interrupt will be triggered when LCMPxIF in the INTFLAGS register is set.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – CMD[1:0]: Timer/Counter Command
These command bits are used for software control of timer/counter update, restart, and reset.
The command bits are always read as zero. The CMD bits must be used together with CMDEN
Table 14-4.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
CMD
00
01
10
11
”Interrupts and Programmable Multilevel Interrupt Controller” on page
”Interrupts and Programmable Multilevel Interrupt Controller” on page
”Interrupts and Programmable Multilevel Interrupt Controller” on page
LCMPDINTLVL[1:0]
R/W
Command selections
7
0
R
7
–
0
Group Configuration
RESTART
R/W
R
6
0
6
–
0
RESET
NONE
—
LCMPCINTLVL[1:0]
R/W
R
5
–
0
5
0
4
–
R
0
Description
None
Reserved
Force restart
Force hard reset (ignored if T/C is not in OFF state)
R/W
4
0
R/W
3
0
LCMPBINTLVL[1:0]
R/W
CMD[1:0]
3
0
Atmel AVR XMEGA B
R/W
2
0
R/W
2
0
R/W
1
0
CMDEN[1:0]
LCMPAINTLVL[1:0]
R/W
1
0
R/W
0
0
R/W
0
0
133. The
133. The
133. The
CTRLF
INTCTRLB
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