ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 27

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.14.9
4.14.10
8291A–AVR–10/11
CTRLB – Control Register B
INTCTRL – Interrupt Control Register
• Bit 0 – CMDEX: Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the config-
uration change protection (CCP) mechanism, refer to
page 12
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 – EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit enables data memory mapping of the EEPROM section. The EEPROM can then
be accessed using load and store instructions.
• Bit 2 – FPRM: Flash Power Reduction Mode
Setting this bit enables power saving for the flash memory. If code is running from the applica-
tion section, the boot loader section will be turned off, and vice versa. If access to the section
that is turned off is required, the CPU will be halted for a time equal to the start-up time from the
idle sleep mode.
• Bit 1 – EPRM: EEPROM Power Reduction Mode
Setting this bit enables power saving for the EEPROM. The EEPROM will then be turned off in a
manner equal to entering sleep mode. If access is required, the bus master will be halted for a
time equal the start-up time from idle sleep mode.
• Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and
cannot be cleared from software. This bit is protected by the configuration change protection
(CCP) mechanism.Refer to
CCP.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x0D
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
for details on the CCP.
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
”Configuration Change Protection” on page 12
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
EEMAPEN
R/W
3
0
R/W
3
0
SPMLVL[1:0]
Atmel AVR XMEGA B
”Configuration Change Protection” on
FPRM
R/W
2
0
R/W
2
0
EPRM
R/W
1
0
R/W
1
0
EELVL[1:0]
SPMLOCK
for details on the
R/W
R/W
0
0
0
0
INTCTRL
CTRLB
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