ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 331

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.9.1
Figure 25-13. ADC timing for one single conversion without gain.
Figure 25-14. ADC timing for one single conversion with increased sampling time (SAMPVAL = 6).
25.9.2
8291A–AVR–10/11
CONVERTING BIT
ADC SAMPLE
CONVERTING BIT
CONVERTING BIT
ADC SAMPLE
START
clk
ADC
Single Conversion without Gain
Single Conversion with Gain
IF
START
clk
ADC
IF
IF
1
Figure 25-13 on page 331
ing of the start conversion bit, or the event triggering the conversion (START), must occur at
least one peripheral clock cycle before the ADC clock cycle on which the conversion starts (indi-
cated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 25-15 on page 332
version with various gain settings. As seen in the
into the ADC. Gain is achieved by running the signal through a pipeline stage without converting.
Compared to a conversion without gain, each gain multiplication of 2 adds one half ADC clock
cycle.
msb
1
msb
10
2
10
9
2
8
9
3
7
8
3
msb
to
shows the ADC timing for a single conversion without gain. The writ-
6
7
4
Figure 25-17 on page 333
10
5
6
4
9
5
4
5
8
3
4
5
7
6
2
3
”Overview” on page
6
1
2
Atmel AVR XMEGA B
5
show the ADC timing for one single con-
6
7
lsb
1
4
lsb
3
7
8
323, the gain stage is built
2
1
8
9
lsb
10
9
331