ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 270

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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21.3
21.3.1
8291A–AVR–10/11
Clock Generation
Internal Clock Generation - The Fractional Baud Rate Generator
The clock used for baud rate generation and for shifting and sampling data bits is generated
internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin.
Five modes of clock generation are supported: normal and double-speed asynchronous mode,
master and slave synchronous mode, and master SPI mode.
Figure 21-2. Clock generation logic, block diagram.
The fractional baud rate generator is used for internal clock generation for asynchronous modes,
synchronous master mode, and master SPI mode operation. The output frequency generated
(f
peripheral clock frequency (f
baud rate (in bits per second) and for calculating the BSEL value for each mode of operation. It
also shows the maximum baud rate versus peripheral clock frequency. BSEL can be set to any
value between 0 and 4095. BSCALE can be set to any value between -7 and +7, and increases
or decreases the baud rate slightly to provide the fractional baud rate scaling of the baud rate
generator.
When BSEL is 0, BSCALE must also be 0. Also, the value 2
of the minimum number of clock cycles a frame requires. For more details, see
Rate Generation” on page
BAUD
PORT_INV
DDR_XCK
XCK
Pin
) is determined by the period setting (BSEL), an optional scale setting (BSCALE), and the
xcko
xcki
f
OSC
Baud Rate
Generator
Register
BSEL
Sync
279.
PER
).
f
Table 21-1 on page 271
BAUD
Detector
Edge
/2
Atmel AVR XMEGA B
/4
contains equations for calculating the
ABS(BSCALE)
/2
must at most be one half
DDR_XCK
CLK2X
0
1
0
1
”Fractional Baud
0
1
1
0
UMSEL [1]
txclk
rxclk
270

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