ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 50

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.3
5.3.1
5.3.2
8291A–AVR–10/11
DMA Transaction
Block Transfer and Repeat
Burst Transfer
Figure 5-1.
A complete DMA read and write operation between memories and/or peripherals is called a
DMA transaction. A transaction is done in data blocks, and the size of the transaction (number of
bytes to transfer) is selectable from software and controlled by the block size and repeat counter
settings. Each block transfer is divided into smaller bursts.
The size of the block transfer is set by the block transfer count register, and can be anything
from 1 byte to 64KB.
A repeat counter can be enabled to set a number of repeated block transfers before a transac-
tion is complete. The repeat is from 1 to 255, and an unlimited repeat count can be achieved by
setting the repeat count to zero.
Since the AVR CPU and DMA controller use the same data buses, a block transfer is divided
into smaller burst transfers. The burst transfer is selectable to 1, 2, 4, or 8 bytes. This means that
if the DMA acquires the data bus and a transfer request is pending, it will occupy the bus until all
bytes in the burst are transferred.
A bus arbiter controls when the DMA controller and the AVR CPU can use the bus. The CPU
always has priority, and so as long as the CPU requests access to the bus, any pending burst
transfer must wait. The CPU requests bus access when it executes an instruction that writes or
reads data to SRAM, I/O memory or EEPROM. For more details on memory access bus arbitra-
tion, refer to
REPCNT
CTRLA
CTRLB
TRFCNT
Enable
Burst
”Data Memory” on page
DMA Overview.
DMA Channel 0
DMA Channel 1
Control Logic
DESTADDR
SRCADDR
TRIGSRC
21.
DMA trigger /
Event
Arbiter
CTRL
Arbitration
Atmel AVR XMEGA B
BUF
R/W Master port
Slave port
Read /
Read
Write
Write
matrix
Bus
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