ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 113

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10. WDT – Watchdog Timer
10.1
10.2
10.3
8291A–AVR–10/11
Features
Overview
Normal Mode Operation
•
•
•
•
•
•
The watchdog timer (WDT) is a system function for monitoring correct program operation. It
makes it possible to recover from error situations such as runaway or deadlocked code. The
WDT is a timer, configured to a predefined timeout period, and is constantly running when
enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset.
The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout
period during which WDT must be reset. If the WDT is reset outside this window, either too early
or too late, a system reset will be issued. Compared to the normal mode, this can also catch sit-
uations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a
CPU-independent clock source, and will continue to operate to issue a system reset even if the
main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be
changed by accident. For increased safety, a fuse for locking the WDT settings is also available.
In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset
from the application code before the timeout occurs, then the WDT will issue a system reset.
There are 11 possible WDT timeout (TO
can be reset at any time during the timeout period. A new WDT timeout period will be started
each time the WDT is reset by the WDR instruction. The default timeout period is controlled by
fuses. Normal mode operation is illustrated in
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s.
Two operation modes:
Configuration lock to prevent unwanted changes
– Normal mode
– Window mode
WDT
) periods, selectable from 8ms to 8s, and the WDT
Figure 10-1 on page
Atmel AVR XMEGA B
114.
113