ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 265

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.7
20.7.1
8291A–AVR–10/11
Register Description
CTRL – Control register
• Bit 7 – CLK2X: Clock Double
When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see
20-3 on page
• Bit 6 – ENABLE: Enable
Setting this bit enables the SPI module. This bit must be set to enable any SPI operations.
• Bit 5 – DORD: Data Order
DORD decides the data order when a byte is shifted out from the DATA register. When DORD is
written to one, the least-significant bit (lsb) of the data byte is transmitted first, and when DORD
is written to zero, the most-significant bit (msb) of the data byte is transmitted first.
• Bit 4 – MASTER: Master Select
This bit selects master mode when written to one, and slave mode when written to zero. If SS is
configured as an input and driven low while master mode is set, master mode will be cleared.
• Bit 3:2 – MODE[1:0]: Transfer Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with
respect to the serial data are shown in
first edge of a clock cycle (leading edge) is rising or falling, and whether data setup and sample
occur on the leading or trailing edge.
When the leading edge is rising, the SCK signal is low when idle, and when the leading edge is
falling, the SCK signal is high when idle.
Table 20-2.
• Bits 1:0 – PRESCALER[1:0]: Clock Prescaler
These two bits control the SPI clock rate configured in master mode. These bits have no effect in
slave mode. The relationship between SCK and the peripheral clock frequency ( clk
shown in
Bit
+0x00
Read/Write
Initial Value
MODE[1:0]
00
01
10
11
Table 20-3 on page
CLK2X
R/W
266).
7
0
SPI transfer modes.
ENABLE
Group Configuration
R/W
6
0
266.
0
1
2
3
DORD
R/W
5
0
Table 20-2 on page
MASTER
R/W
4
0
Leading Edge
Rising, sample
Rising, setup
Falling, sample
Falling, setup
R/W
3
0
MODE[1:0]
Atmel AVR XMEGA B
265. These bits decide whether the
R/W
2
0
R/W
PRESCALER[1:0]
1
0
Trailing Edge
Falling, setup
Falling, sample
Rising, setup
Rising, sample
R/W
0
0
PER
CTRL
Table
265
) is