ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 165

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.12 Register Description
13.12.1
13.12.2
8291A–AVR–10/11
CTRLA – Control register A
CTRLB – Control register B
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CLKSEL[3:0]: Clock Select
These bits select the clock source for the timer/counter according to
CLKSEL=0001 must be set to ensure a correct output from the waveform generator when the hi-
res extension is enabled.
Table 13-3.
• Bit 7:4 – CCxEN: Compare or Capture Enable
Setting these bits in the FRQ or PWM waveform generation mode of operation will override the
port output register for the corresponding OCn output pin.
When input capture operation is selected, the CCxEN bits enable the capture operation for the
corresponding CC channel.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
CLKSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1nnn
CCDEN
R/W
Clock select options.
7
0
R
7
–
0
Group Configuration
CCCEN
R/W
R
6
0
6
–
0
DIV1024
DIV256
EVCHn
DIV64
DIV1
DIV2
DIV4
DIV8
OFF
CCBEN
R/W
R
5
0
5
–
0
CCAEN
R/W
R
4
0
4
–
0
Description
None (i.e, timer/counter in OFF state)
Prescaler: Clk
Prescaler: Clk/2
Prescaler: Clk/4
Prescaler: Clk/8
Prescaler: Clk/64
Prescaler: Clk/256
Prescaler: Clk/1024
Event channel n, n= [0,...,3]
R/W
R
3
0
3
–
0
Atmel AVR XMEGA B
R/W
R/W
2
0
2
0
CLKSEL[3:0]
WGMODE[2:0]
Table
R/W
R/W
1
0
1
0
13-3.
R/W
R/W
0
0
0
0
CTRLA
CTRLB
165