ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 64

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.15
5.16
5.17
Table 5-14.
8291A–AVR–10/11
Address
Address
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x10
+0x20
+0x30
+0x40
+0x0A
+0x0B
+0x0C
+0x0D
+0x0E
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x0F
Offset
0x00
0x02
Register Summary – DMA Controller
Register Summary – DMA Channel
DMA Interrupt Vector Summary
Name
Name
DESTADDR0
DESTADDR1
SRCADDR0
SRCADDR1
INTFLAGS
CH0 Offset
CH1 Offset
DMA interrupt vectors and their word offset addresses from the DMA controller interrupt base.
ADDCTRL
TRFCNTH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRIGSRC
TRFCNTL
Reserved
Reserved
Reserved
Reserved
Reserved
STATUS
REPCNT
CTRLA
CTRLB
TEMP
CTRL
CH0_vect
CH1_vect
ENABLE
CHBUSY
Source
Bit 7
Bit 7
CHEN
–
–
–
–
–
–
–
–
–
–
–
–
–
SRCRELOAD[1:0]
CHPEND
RESET
CHRST
Bit 6
Bit 6
–
–
–
–
–
–
–
–
–
–
–
–
–
Interrupt Description
DMA controller channel 0 interrupt vector
DMA controller channel 1 interrupt vector
CH1ERRIF
CH1BUSY
REPEAT
Bit 5
Bit 5
ERRIF
–
–
–
–
–
–
–
–
–
–
–
–
SRCDIR[1:0]
Offset address for DMA Channel 0
Offset address for DMA Channel 1
CH0ERRIF
CH0BUSY
TRFREQ
Bit 4
TRNIF
Bit 4
–
–
–
–
–
–
–
–
–
–
–
–
DESTADDR[15:8]
SRCADDR[15:8]
DESTADDR[7:0]
SRCADDR[7:0]
TRIGSRC[7:0]
TRFCNT[15:8]
TRFCNT[7:0]
REPCNT[7:0]
TEMP[7:0]
Bit 3
Bit 3
–
–
–
–
–
–
–
–
–
DESTRELOAD[1:0]
–
–
–
–
–
–
ERRINTLVL[1:0]
DBUFMODE
SINGLE
Atmel AVR XMEGA B
Bit 2
Bit 2
–
–
–
–
–
–
–
–
–
–
–
–
–
CH1TRNFIF
CH1PEND
Bit 1
Bit 1
–
–
–
–
–
–
–
–
–
–
–
–
BURSTLEN[1:0]
TRNINTLVL[1:0]
DESTDIR[1:0]
CH0TRNFIF
CH0PEND
PRIMODE
Bit 0
Bit 0
–
–
–
–
–
–
–
–
–
–
–
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