ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 339

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.15.5
8291A–AVR–10/11
PRESCALER – Clock Prescaler register
• Bit 2:0 – EVACT[2:0]: Event Mode
These bits select and limit how many of the selected event input channel are used, and also fur-
ther limit the ADC channels triggers. They also define more special event triggers as defined in
Table 25-5 on page
Table 25-5.
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2:0 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to
339.
Table 25-6.
Bit
+0x04
Read/Write
Initial Value
PRESCALER[2:0]
EVACT[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
R
7
–
0
ADC event mode select.
ADC prescaler settings .
339.
R
6
–
0
Group Configuration
SYNCSWEEP
Group Configuration
NONE
R
5
–
0
CH0
–
–
–
–
–
DIV128
DIV256
DIV512
DIV16
DIV32
DIV64
DIV4
DIV8
R
4
–
0
Event Input Operation Mode
No event inputs
Event channel with the lowest number defined by
EVSEL triggers conversion on ADC channel
Reserved
Reserved
Reserved
Reserved
The ADC is flushed and restarted for accurate timing
Reserved
R
3
–
0
Atmel AVR XMEGA B
R/W
Peripheral Clock Division Factor
2
0
PRESCALER[2:0]
R/W
1
0
128
256
512
16
32
64
4
8
Table 25-6 on page
R/W
0
0
PRESCALER
339