ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 258

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.4
8291A–AVR–10/11
ADDR
–
Address register
• Bit 4
This flag contains the most recently received acknowledge bit from the master. This is a read-
only flag. When read as zero, the most recent acknowledge bit from the maser was ACK, and
when read as one, the most recent acknowledge bit was NACK.
• Bit 3
This flag is set when a slave has not been able to transfer a high data bit or a NACK bit. If a col-
lision is detected, the slave will commence its normal operation, disable data, and acknowledge
output, and no low values will be shifted out onto the SDA line. Writing a one to this bit location
will clear COLL.
The flag is also cleared automatically when a START or repeated START condition is detected.
• Bit 2
This flag is set when an illegal bus condition occurs during a transfer. An illegal bus condition
occurs if a repeated START or a STOP condition is detected,and the number of bits from the
previous START condition is not a multiple of nine. Writing a one to this bit location will clear
BUSERR.
For bus errors to be detected, the bus state logic must be enabled. This is done by enabling the
TWI master.
• Bit 1
The R/W direction (DIR) flag reflects the direction bit from the last address packet received from
a master. When this bit is read as one, a master read operation is in progress. When read as
zero, a master write operation is in progress.
• Bit 0
This flag indicates whether a valid address or a STOP condition caused the last setting of APIF
in the STATUS register.
Table 19-9.
This register contains the TWI slave address used by the slave address match logic to deter-
mine if a master has addressed the slave. The seven most-significant bits (ADDR[7:1])
represent the slave address and the least-significant bit (ADDR[0]) is used for general call
address recognition.
When ADDR[0] is set, this enables general call address recognition logic so the device can
respond to a general address call that addresses all devices on the bus.
Bit
+0x03
Read/Write
Initial Value
AP
0
1
–
–
–
–
–
RXACK: Received Acknowledge
COLL: Collision
BUSERR: TWI Slave Bus Error
DIR: Read/Write Direction
AP: Slave Address or Stop
R/W
TWI slave address or stop.
7
0
Description
A STOP condition generated the interrupt on APIF
Address detection generated the interrupt on APIF
R/W
6
0
R/W
5
0
ADDR[7:1]
R/W
4
0
R/W
3
0
Atmel AVR XMEGA B
R/W
2
0
R/W
1
0
ADDR[0]
R/W
0
0
ADDR
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