ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 167

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.12.4
8291A–AVR–10/11
CTRLD – Control register D
• Bit 7:5 – EVACT[2:0]: Event Action
These bits define the event action the timer will perform on an event according to
page
The EVSEL setting will decide which event source or sources have control in this case.
Table 13-5.
Selecting any of the capture event actions changes the behaviour of the CCx registers and
related status and control bits to be used for capture. The error status flag (ERRIF) will indicate a
buffer overflow in this configuration.
• Bit 4 – EVDLY: Timer Delay Event
When this bit is set, the selected event source is delayed by one peripheral clock cycle. This is
intended for 32-bit input capture operation. Adding the event delay is necessary to compensate
for the carry propagation delay when cascading two counters via the event system.
• Bit 3:0 – EVSEL[3:0]:Timer Event Source Select
These bits select the event channel source for the timer/counter. For the selected event channel
to have any effect, the event action bits (EVACT) must be set according to
event action is set to a capture operation, the selected event channel n will be the event channel
source for CC channel A, and event channel (n+1)%4, (n+2)%4, and (n+3)%4 will be the event
channel source for CC channel B, C, and D.
Bit
+0x03
Read/Write
Initial Value
167.
EVACT[2:0]
000
001
010
011
100
101
110
111
Timer event action selection.
R/W
7
0
EVACT[2:0]
R/W
6
0
Group Configuration
UPDOWN
RESTART
R/W
QDEC
CAPT
5
0
FRQ
OFF
PW
EVDLY
R/W
4
0
Event Action
None
Input capture
Externally controlled up/ down count
Quadrature decode
Restart waveform period
Frequency capture
Pulse width capture
Reserved
R/W
3
0
Atmel AVR XMEGA B
R/W
2
0
EVSEL[3:0]
R/W
1
0
Table
R/W
13-5. When the
0
0
Table 13-5 on
CTRLD
167