ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 363

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.4.3
27.4.4
27.4.5
27.4.6
27.4.7
8291A–AVR–10/11
SAMPLE/PRELOAD; 0x2
BYPASS; 0xf
CLAMP; 0x4
HIGHZ; 0x5
PDICOM; 0x7
The active states are:
SAMPLE/PRELOAD is the instruction for preloading the output latches and taking a snapshot of
the input/output pins without affecting system operation. However, the output latches are not
connected to the pins. The boundary scan chain is selected as the data register. Since each of
the SAMPLE and PRELOAD instructions implements the functionality of the other, they share a
common binary value, and can be treated as a single, merged instruction.
The active states are:
BYPASS is the instruction for selecting the bypass register for the data register. This instruction
can be issued to make the shortest possible scan chain through the device.
The active states are:
CLAMP is an optional instruction that allows the state of the input/output pins to be determined
from the preloaded output latches. The instruction allows static pin values to be applied via the
boundary scan registers while bypassing these registers in the scan path, efficiently shortening
the total length of the serial test path. The bypass register is selected as the data register.
The active states are:
HIGHZ is an optional instruction for putting all outputs in an inactive drive state (e.g., high imped-
ance). The bypass register is selected as the data register.
The active states are:
PDICOM is an AVR XMEGA specific instruction for using the JTAG TAP as an alternative inter-
face to the PDI.
• Capture DR: Data in the IDCODE register are sampled into the device identification register
• Shift DR: The IDCODE scan chain is shifted by the TCK input
• Capture DR: Data on the external pins are sampled into the boundary scan chain
• Shift DR: The boundary scan chain is shifted by the TCK input
• Update DR: Data from the boundary scan chain are applied to the output latches, but the
• Capture DR: Loads a zero into the bypass register
• Shift DR: The bypass register cell between TDI and TDO is shifted
• Capture DR: Loads a zero into the bypass register
• Shift DR: The bypass register cell between TDI and TDO is shifted
• Capture DR: Loads a zero into the bypass register
• Shift DR: The bypass register cell between TDI and TDO is shifted
output latches are not connected to the pins
Atmel AVR XMEGA B
363