ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 239

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.1
19.3.2
8291A–AVR–10/11
Electrical Characteristics
START and STOP Conditions
Figure 19-2. Basic TWI transaction diagram topology for a 7-bit address bus .
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low-level period of the clock to decrease the clock speed.
The TWI module in XMEGA devices follows the electrical specifications and timing of I
and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior,
the inactive bus timeout period should be set in TWI master mode. Refer to
tion” on page 244
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition (S) by indicating a high-to-low transition on
the SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low-to-high transition on the SDA line while SCL line is kept
high.
Figure 19-3. START and STOP conditions.
Multiple START conditions can be issued during a single transaction. A START condition that is
not directly following a STOP condition is called a repeated START condition (Sr).
SDA
SCL
SDA
SCL
S
The master provides data on the bus
The master or slave can provide data on the bus
The slave provides data on the bus
S
Condition
START
for more details.
ADDRESS
ADDRESS
S
6 ... 0
Address Packet
R/W
R/W
A
Direction
ACK
Data Packet #0
Transaction
DATA
DATA
7 ... 0
Atmel AVR XMEGA B
ACK
A
Data Packet #1
DATA
DATA
7 ... 0
”TWI Master Opera-
ACK/NACK
Condition
A/A
STOP
P
P
P
2
C bus
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