ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 115

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.6
10.7
10.7.1
8291A–AVR–10/11
Configuration Protection and Lock
Registers Description
CTRL – Control register
The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT
settings.
The first mechanism is the configuration change protection mechanism, employing a timed write
procedure for changing the WDT control registers. In addition, for the new configuration to be
written to the control registers, the register’s change enable bit must be written at the same time.
The second mechanism locks the configuration by setting the WDT lock fuse. When this fuse is
set, the watchdog time control register cannot be changed; hence, the WDT cannot be disabled
from software. After system reset, the WDT will resume at the configured operation. When the
WDT lock fuse is programmed, the window mode timeout period cannot be changed, but the
window mode itself can still be enabled or disabled.
• Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:2 – PER[3:0]: Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In
window mode operation, these bits define the open window period. The different typical timeout
periods are found in
period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are
protected by the configuration change protection mechanism. For a detailed description, refer to
”Configuration Change Protection” on page
Table 10-1.
Bit
+0x00
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
PER[3:0]
0000
0001
0010
0011
0100
0101
Watchdog timeout periods .
R
R
7
–
0
Table
R
R
6
–
0
10-1. The initial values of these bits are set by the watchdog timeout
Group Configuration
R/W
R
X
5
128CLK
256CLK
16CLK
32CLK
64CLK
8CLK
R/W
R
4
X
12.
PER[3:0]
R/W
R
X
3
Atmel AVR XMEGA B
R/W
R
2
X
Typical Timeout Periods
ENABLE
R/W
R
X
1
0.128s
0.256s
16ms
32ms
64ms
8ms
CEN
R/W
R
0
0
CTRL
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