ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 311

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.2
8291A–AVR–10/11
CTRLB – Control Register B
• Bit 3 – SEGSWP: Segment Terminal Bus Swap
Writing this bit to one inverts completely the order of the segment terminal bus (SEG[39:0]). The
segment terminals un-selected by PMSK[5:0] are also affected (see
Table 24-5.
Note:
• Bit 2 – CLRDT: Clear Data Register
Writing this bit to one clears immediately the Display Memory (but not the control registers). The
display will be blanked after completion of a frame. This bit is automatically reset once the Dis-
play Memory is cleared.
• Bit 1 – SEGON: Segments “ON”.
Writing this bit to one enables all segments and the contents of the Display Memory is output on
the LCD. Writing it to zero, turns “OFF” all LCD segments.
This bit can be used to flash the LCD, leaving the LCD timing generator enabled.
• Bit 0 – BLANK: Blanking Display Mode
When this bit is written to one, the display will be blanked after completion of a frame. All seg-
ment and common terminals will be driven to ground. (For more details see
on page
• Bit 7 – PRESC: LCD Prescaler Select
The PRESC bit selects a tap point from a ripple counter. The ripple counter output can be further
divided by setting the Clock Divider (CLKDIV[2:0]). The different selections are shown in
24-6 on page
the LCD controller.
Bit
+0x01
Read/Write
Initial Value
PMSK[5:0]
000100
001000
010000
101000
1. Refer to specific device datasheet for availability of this feature.
307). This function does not modify the Display Memory.
PRESC
R/W
7
0
Number of SEG
312. Together they define the prescaler LCD clock (clk
Segment Terminal Bus Reverse (examples)
16
40
4
8
R/W
6
0
CLKDIV[2:0]
R/W
SEGSWP = 0
(SEG [39:4] unused), SEG[3:0]
(SEG[39:8] unused), SEG[7:0]
(SEG[39:16] unused), SEG[15:0]
SEG[39:0]
5
0
R/W
4
0
LPWAV
R/W
3
0
(1)
Atmel AVR XMEGA B
R
2
–
0
SEGSWP = 1
SEG[0:3], (SEG[4:39] unused)
SEG[0:7], (SEG[8:39] unused)
SEG[0:15], (SEG[16:39] unused)
SEG[0:39]
Table 24-5 on page
R/W
LCD_PS
1
0
DUTY[1:0]
), which is clocking
”Display Blanking”
R/W
0
0
311).
CTRLB
Table
311